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PE3342 Datasheet(PDF) 11 Page - Peregrine Semiconductor Corp. |
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PE3342 Datasheet(HTML) 11 Page - Peregrine Semiconductor Corp. |
11 / 17 page Product Specification PE3342 Page 11 of 17 Document No. 70-0091-03 │ www.psemi.com ©2005 Peregrine Semiconductor Corp. All rights reserved. Gross EEPROM Programming Timing Grid Figure 7 shows a gross PE3342 EEPROM programming timing grid although each individual step has been described thoroughly in previous sections. It starts with EE Register load, and then together with other parameters a Vpp_ERASE negative pulse is applied to Vpp pin to erase the EEPROM contents and followed by a Vpp_WRITE pulse for EEPROM write cycle. The separation between the Vpp_ERASE and Vpp_WRITE pulse has to be at least 100 ms if mechanical relays are used to avoid both being on at the same time. After EE programming, the contents of the EEPROM cells can be verified by setting Enhancement Register Bit 1. A procedure shown in Figure 8 is applied twice. The first time is to load the EE Register from EEPROM and the second time is to shift out the EE Register contents through Dout pin. Figure 7. Gross PE3342 EEPROM Programming Timing Grid Data S_WR Vpp_ERASE Vpp_WRITE 0V 3V 0V 3V 0V 12.5V 0V -8.5V 25 ms 25 ms EE Register load EE PROM Erase EE PROM Write 0V 40 ms E_WR 0V 3V EELoa d 3V EESel 0V 3V Clock 0V 3V Dout 0V 3V >=100 ms Rough time scale The final set of Dout is EEPROM content Note: ENH/ ( Pin 3 in TSSOP or Pin 20 in QFN) is at low (0) for this process. EE Register shifted out through Dout CHANNEL CODE ENH code set's Dout mux to EE EE Register load from EEPROM |
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