3340-12 datasheet(2/12 Pages) PEREGRINE

Part #	3340-12

Description	3.0 GHz Integer-N PLL for Low Phase Noise Applications

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Manufacturer	PEREGRINE [Peregrine Semiconductor Corp.]

Direct Link	http://www.peregrine-semi.com

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PE3340

Advance Information

Copyright

File No. 70/0040~02A

|

UTSi ® CMOS RFIC SOLUTIONS

Page 2 of 12

Figure 2. Pin Configuration

Table 1. Pin Descriptions

Pin No.

Pin Name

Type

Description

1

VDD

(Note 1)

Power supply input. Input may range from 2.85 V to 3.15 V. Bypassing required.

2

Enh

Input

Enhancement mode. When asserted low (“0”), enhancement register bits are functional. Internal 70 k

Ω pull-up

resistor.

3

S_WR

Input

Serial load enable input. While S_WR is “low”, Sdata can be serially clocked. Primary register data are

transferred to the secondary register on S_WR rising edge.

4

Sdata

Input

Binary serial data input. Input data entered MSB first.

5

Sclk

Input

Serial clock input. Sdata is clocked serially into the 20-bit primary register (E_WR “low”) or the 8-bit

enhancement register (E_WR “high”) on the rising edge of Sclk.

6

GND

Ground.

7

FSELS

Input

Selects contents of primary register (FSELS=1) or secondary register (FSELS=0) for programming of internal

counters. Internal 70 k

Ω pull-down resistor.

8

E_WR

Input

Enhancement register write enable. While E_WR is “high”, Sdata can be serially clocked into the enhancement

register on the rising edge of Sclk. Internal 70 k

Ω pull-down resistor.

9

VDD

(Note 1)

Same as pin 1.

10

Fin

Input

Prescaler input from the VCO. Max frequency input is 3.0 GHz.

11

Fin

Input

Prescaler complementary input. A bypass capacitor should be placed as close as possible to this pin and be

connected in series with a 50

Ω resistor to the ground plane.

12

GND

Ground.

13

Cext

Output

Logical “NAND” of PD_U and PD_D terminated through an on chip, 2 k

Ω series resistor. Connecting Cext to an

external capacitor will low pass filter the input to the inverting amplifier used for driving LD.

14

LD

Output

Lock detect is an open drain logical inversion of CEXT. When the loop is in lock, LD is high impedance,

otherwise LD is a logic low (“0”).

15

Dout

Output

Data out function, Dout, enabled in enhancement mode.

16

VDD

(Note 1)

Same as pin 1.

V

DD

1

Enh

2

S_WR

3

Sdata

4

Sclk

5

GND

6

FSELS

7

E_WR

8

V

DD

9

F

in

10

F

in

11

GND

12

Cext

13

LD

14

Dout

15

V

DD

16

PD_D

17

PD_U

18

GND

19

f

r

20

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