Product Specification

PE3335

Page 9 of 15

Document No. 70-0049-02

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©2005 Peregrine Semiconductor Corp. All rights reserved.

The enhancement register is double buffered to

prevent inadvertent control changes during serial

loading, with buffer capture of the serially entered

data performed on the falling edge of E_WR

according to the timing diagram shown in Figure

5. After the falling edge of E_WR, the data provide

control bits as shown in Table 8 with bit

functionality enabled by asserting the

Enh input

“low”.

Direct Interface Mode

Direct Interface Mode is selected by setting the

Bmode input “high”.

Counter control bits are set directly at the pins as

shown in Table 7. In Direct Interface Mode, main

MSB (first in)

(last in) LSB

Table 7. Primary Register Programming

Table 8. Enhancement Register Programming

*Serial data clocked serially on Sclk rising edge while E_WR “low” and captured in secondary register on S_WR rising edge.

*Serial data clocked serially on Sclk rising edge while E_WR “high” and captured in the double buffer on E_WR falling edge.

MSB (first in)

(last in) LSB

Interface

Mode

Enh

Bmode

Smode

Pre_en

Parallel

1

0

0

M2_WR rising edge load

M1_WR rising edge load

A_WR rising edge load

Serial*

1

0

1

Direct

1

1

X

0

0

0

0

Pre_en

Interface

Mode

Enh

Bmode

Smode

Reserved

Reserved

Reserved

Power

down

Counter

load

MSEL

output

Prescaler

output

Parallel

0

X

0

E_WR rising edge load

Serial*

0

X

1