Product Specification

PE3335

Page 6 of 15

©2005 Peregrine Semiconductor Corp. All rights reserved.

Document No. 70-0049-02

│ UltraCMOS™ RFIC Solutions

Symbol

Parameter

Conditions

Min

Max

Units

Control Interface and Latches (see Figures 3, 4, 5)

Serial data clock frequency

10

MHz

Serial clock HIGH time

30

ns

Serial clock LOW time

30

ns

Sdata set-up time after Sclk rising edge, D[7:0] set-up time

to M1_WR, M2_WR, A_WR, E_WR rising edge

10

ns

Sdata hold time after Sclk rising edge, D[7:0] hold time to

M1_WR, M2_WR, A_WR, E_WR rising edge

10

ns

S_WR, M1_WR, M2_WR, A_WR, E_WR pulse width

30

ns

Sclk rising edge to S_WR rising edge. S_WR, M1_WR,

M2_WR, A_WR falling edge to Hop_WR rising edge

30

ns

Sclk falling edge to E_WR transition

30

ns

S_WR falling edge to Sclk rising edge. Hop_WR falling

edge to S_WR, M1_WR, M2_WR, A_WR rising edge

30

ns

E_WR transition to Sclk rising edge

30

ns

MSEL data out delay after Fin rising edge

8

ns

Main Divider (Including Prescaler)

Operating frequency

500

3000

MHz

Input level range

External AC coupling

-5

5

dBm

Main Divider (Prescaler Bypassed)

Operating frequency

50

300

MHz

Input level range

External AC coupling

-5

5

dBm

Reference Divider

Operating frequency

(Note 1)

(Note 2)

100

MHz

Reference input power

Single ended input

-2

10

dBm

Input sensitivity

External AC coupling

(Note 3)

0.5

Phase Detector

Comparison frequency

(Note 1)

20

MHz

Note 1:

Parameter is guaranteed through characterization only and is not tested.

Note 2:

Running at low frequencies (< 10 MHz sinewave), the device will still be functional but may cause phase noise degradation. Inserting a low-

noise amplifier to square up the edges is recommended at lower input frequencies.

Note 3:

CMOS logic levels may be used if DC coupled. For optimum phase noise performance, the reference input falling edge rate should be faster

than 80mV/ns.