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ICS853052AGT Datasheet(PDF) 8 Page - Integrated Circuit Systems

Part # ICS853052AGT
Description  DUAL LVCMOS / LVTTL-TO-DIFFERENTIAL 2.5V, 3.3V, 5V LVPECL MULTIPLEXER
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Manufacturer  ICST [Integrated Circuit Systems]
Direct Link  http://www.icst.com
Logo ICST - Integrated Circuit Systems

ICS853052AGT Datasheet(HTML) 8 Page - Integrated Circuit Systems

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853052AG
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REV. A JULY 1, 2004
8
Integrated
Circuit
Systems, Inc.
ICS853052
DUAL LVCMOS / LVTTL-TO-DIFFERENTIAL
2.5V, 3.3V, 5V LVPECL MULTIPLEXER
PRELIMINARY
The clock layout topology shown below is a typical termina-
tion for LVPECL outputs. The two different layouts mentioned
are recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that gen-
erate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must
be used for functionality. These outputs are designed to drive
50
Ω transmission lines. Matched impedance techniques should
be used to maximize operating frequency and minimize signal
distortion.
Figures 2A and 2B show two different layouts which
are recommended only as guidelines. Other suitable clock lay-
outs may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
TERMINATION FOR 3.3V LVPECL OUTPUTS
FIGURE 2B. LVPECL OUTPUT TERMINATION
FIGURE 2A. LVPECL OUTPUT TERMINATION
V
CC - 2V
50
50
RTT
Z
o = 50Ω
Z
o = 50Ω
FOUT
FIN
RTT =
Z
o
1
((V
OH + VOL) / (VCC – 2)) – 2
3.3V
125
125
84
84
Z
o = 50Ω
Z
o = 50Ω
FOUT
FIN
TERMINATION FOR 5V LVPECL OUTPUT
This section shows examples of 5V LVPECL output termina-
tion.
Figure 3A shows standard termination for 5V LVPECL. The
termination requires matched load of 50
Ω resistors pull down to
Zo = 50 Ohm
R2
50
Zo = 50 Ohm
5V
3V
PECL
+
-
R1
50
5V
PECL
R4
84
5V
Zo = 50 Ohm
R3
84
R2
125
5V
PECL
PECL
+
-
Zo = 50 Ohm
R1
125
FIGURE 3A. STANDARD 5V PECL OUTPUT TERMINATION
FIGURE 3B. 5V PECL OUTPUT TERMINATION EXAMPLE
V
CC - 2V = 3V at the receiver. Figure 3B shows Thevenin equiva-
lence of Figure 3A. In actual application where the 3V DC power
supply is not available, this approached is normally used.


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