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ICSSSTV16857CG-T Datasheet(PDF) 6 Page - Integrated Circuit Systems

Part # ICSSSTV16857CG-T
Description  DDR 14-Bit Registered Buffer
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Manufacturer  ICST [Integrated Circuit Systems]
Direct Link  http://www.icst.com
Logo ICST - Integrated Circuit Systems

ICSSSTV16857CG-T Datasheet(HTML) 6 Page - Integrated Circuit Systems

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6
ICSSSTV16857C
0002F—10/25/02
Notes:
1. CL incluces probe and jig capacitance.
2. IDD tested with clock and data inputs held at VDDQ or GND, and IO = 0 mA.
3. All input pulses are supplied by generators having the following characteristics: PRR @10 MHz,
Zo=50
Ω, input slew rate = 1 V/ns ±20% (unless otherwise specified).
4. The outputs are measured one at a time with one transition per measurement.
5. VTT = VREF = VDDQ/2
6. VIH = VREF + 310mV (AC voltage levels) for differential inputs. VIH = VDDQ for LVCMOS input.
7. VIL = VREF - 310mV (AC voltage levels) for differential inputs. VIL = GND for LVCMOS input.
8. tPLH and tPHL are the same as tpd
Test Point
Load Circuit
From Output
Under Test
C= 30 pF
(see Note 1)
L
VTT
R =
L 50Ω
LVCMOS
RESET#
Input
LVCMOS
RESET#
Input
V
DDQ
/2
V
DDQ
/2
tinact
tact
I
(see note 2)
DD
IDDH
IDDL
10%
90%
Voltage and Current Waveforms
Inputs Active and Inactive Times
Voltage Waveforms - Propagation Delay Times
Voltage Waveforms - Propagation Delay Times
Figure 1 - Parameter Measurement Information (V
DDQ = 2.5V ±0.2V)
Voltage Waveforms - Pulse Duration
Voltage Waveforms - Setup and Hold Times
VDDQ
0V
t
w
t
S
t
h
VIH
VIH
VOH
VTT
VTT
VTT
VOH
VIH
VIL
VIL
VOL
VOL
VI(pp)
VI(pp)
VIL
VREF
VREF
VREF
VREF
VICR
VICR
tPHL
tPHL
tPHL
V/2
DD
VICR
Input
Input
Timing
Input
Timing
Input
Output
Output


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