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ICS844051CGIT Datasheet(PDF) 7 Page - Integrated Circuit Systems |
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ICS844051CGIT Datasheet(HTML) 7 Page - Integrated Circuit Systems |
7 / 11 page 844051CGI www.icst.com/products/hiperclocks.html REV. A NOVEMBER 23, 2005 7 Integrated Circuit Systems, Inc. ICS844051I FEMTOCLOCKS™ CRYSTAL-TO- LVDS CLOCK GENERATOR PRELIMINARY APPLICATION INFORMATION Figure 2. CRYSTAL INPUt INTERFACE CRYSTAL INPUT INTERFACE The ICS844051I has been characterized with 18pF parallel resonant crystals. The capacitor values, C1 and C2, shown in Figure 2 below were determined using a 25MHz, 18pF parallel resonant crystal and were chosen to minimize the ppm error. The optimum C1 and C2 values can be slightly adjusted for dif- ferent board layouts. POWER SUPPLY FILTERING TECHNIQUES As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS844051I provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. V DD and VDDA should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 1 illustrates how a 10 Ω resistor along with a 10μF and a .01μF bypass capacitor should be connected to each V DDA pin. The 10Ω resistor can also be replaced by a ferrite bead. FIGURE 1. POWER SUPPLY FILTERING 10 Ω V DDA 10 μF .01 μF 3.3V or 2.5V .01 μF V DD C1 X1 Crystal C2 XTAL_IN XTAL_OUT |
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