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ICS844031AGI-01T Datasheet(PDF) 8 Page - Integrated Circuit Systems |
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ICS844031AGI-01T Datasheet(HTML) 8 Page - Integrated Circuit Systems |
8 / 12 page 844031AGI-01 www.icst.com/products/hiperclocks.html REV. B JULY 6, 2005 8 Integrated Circuit Systems, Inc. ICS844031I-01 FEMTOCLOCKS™CRYSTAL-TO- LVDS CLOCK GENERATOR PRELIMINARY 3.3V, 2.5V LVDS DRIVER TERMINATION A general LVDS interface is shown in Figure 3. In a 100 Ω differential transmission line environment, LVDS drivers require a matched load termination of 100 Ω across near FIGURE 3. TYPICAL LVDS DRIVER TERMINATION the receiver input. For a multiple LVDS outputs buffer, if only partial outputs are used, it is recommended to terminate the un-used outputs. 2.5V or 3.3V + - VDD 100 Ohm Differential Transmission Line R1 100 LVDS_Driv er |
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