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ICS3726M-02 Datasheet(PDF) 3 Page - Integrated Circuit Systems |
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ICS3726M-02 Datasheet(HTML) 3 Page - Integrated Circuit Systems |
3 / 6 page HIGH PERFORMANCE VCXO MDS 3726-02 B 3 Revision 120505 In te gr ated Circuit Systems ● 525 Ra ce Street, San Jose, CA 9512 6 ● tel (4 08) 297-1 201 ● www.icst.com ICS3726-02 PRELIMINARY INFORMATION External Component Selection The ICS3726-02 requires a minimum number of external components for proper operation. Decoupling Capacitors A decoupling capacitor of 0.01 µF should be connected between VDD and GND on pins 6 and 4 as close to the ICS3726-02 as possible. For optimum device performance, the decoupling capacitor should be mounted on the component side of the PCB. Avoid the use of vias in the decoupling circuit. Series Termination Resistor When the PCB trace between the clock output and the load is over 1 inch, series termination should be used. To series terminate a 50 Ω trace (a commonly used trace impedance), place a 33 Ω resistor in series with the clock line, as close to the clock output pin as possible. The nominal impedance of the clock output is 20 Ω. Quartz Crystal The ICS3726-02 VCXO function consists of the external crystal and the integrated VCXO oscillator circuit. To assure the best system performance (frequency pull range) and reliability, a crystal device with the recommended parameters (shown below) must be used, and the layout guidelines discussed in the following section shown must be followed. The oscillation frequency of a quartz crystal is determined by its “cut” and by the load capacitors connected to it. The ICS3726-02 incorporates on-chip variable load capacitors that pull (change) the frequency of the crystal. The crystal specified for use with the ICS3726-02 is designed to have zero frequency error when the total of on-chip + stray capacitance is 10 pF. Recommended Crystal Parameters: Initial Accuracy at 25°C ±20 ppm Temperature Stability ±30 ppm Aging ±20 ppm Load Capacitance 14 pF Shunt Capacitance, C0 7 pF max C0/C1 Ratio 250 max Equivalent Series Resistance 35 Ω max The external crystal must be connected as close to the chip as possible and should be on the same side of the PCB as the ICS3726-02. There should be no via’s between the crystal pins and the X1 and X2 device pins. There should be no signal traces underneath or close to the crystal. See application note MAN05. Crystal Tuning Load Capacitors The crystal traces should include pads for small fixed capacitors, one between X1 and ground, and another between X2 and ground. Stuffing of these capacitors on the PCB is optional. The need for these capacitors is determined at system prototype evaluation, and is influenced by the particular crystal used (manufacture and frequency) and by PCB layout. The typical required capacitor value is 1 to 4 pF. This chip has internal load capacitors and is designed to work with surface mount crystals with 10 pF load capacitance. The procedure for determining the value of these capacitors can be found in application note MAN05. |
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