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023AI Datasheet(PDF) 7 Page - Integrated Circuit Systems |
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023AI Datasheet(HTML) 7 Page - Integrated Circuit Systems |
7 / 13 page 843023AGI www.icst.com/products/hiperclocks.html REV. A JUNE 29, 2005 7 Integrated Circuit Systems, Inc. ICS843023I FEMTOCLOCKS™CRYSTAL-TO-3.3V, 2.5V LVPECL CLOCK GENERATOR APPLICATION INFORMATION Figure 1. CRYSTAL INPUt INTERFACE CRYSTAL INPUT INTERFACE The ICS843023I has been characterized with 18pF parallel resonant crystals. The capacitor values, C1 and C2, shown in Figure 1 below were determined using a 25MHz, 18pF parallel resonant crystal and were chosen to minimize the ppm error. The optimum C1 and C2 values can be slightly adjusted for different board layouts. TERMINATION FOR 3.3V LVPECL OUTPUT The clock layout topology shown below is a typical termina- tion for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs.Therefore, terminat- ing resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to FIGURE 2B. LVPECL OUTPUT TERMINATION FIGURE 2A. LVPECL OUTPUT TERMINATION drive 50 Ω transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 2A and 2B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. V CC - 2V 50 Ω 50 Ω RTT Z o = 50Ω Z o = 50Ω FOUT FIN RTT = Z o 1 ((V OH + VOL) / (VCC – 2)) – 2 3.3V 125 Ω 125 Ω 84 Ω 84 Ω Z o = 50Ω Z o = 50Ω FOUT FIN C1 33p X1 18pF Parallel Crystal C2 22p XTAL_OUT XTAL_IN |
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