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ICS843003AI01 Datasheet(PDF) 10 Page - Integrated Circuit Systems |
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ICS843003AI01 Datasheet(HTML) 10 Page - Integrated Circuit Systems |
10 / 13 page 843003AGI-01 www.icst.com/products/hiperclocks.html REV. A MAY 26, 2005 10 Integrated Circuit Systems, Inc. ICS843003I-01 FEMTOCLOCKS™CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER PRELIMINARY TERMINATION FOR 3.3V LVPECL OUTPUT V CC - 2V 50 Ω 50 Ω RTT Z o = 50Ω Z o = 50Ω FOUT FIN RTT = Z o 1 ((V OH + VOL) / (VCC – 2)) – 2 3.3V 125 Ω 125 Ω 84 Ω 84 Ω Z o = 50Ω Z o = 50Ω FOUT FIN The clock layout topology shown below is a typical termi- nation for LVPECL outputs. The two different layouts men- tioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, ter- minating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are FIGURE 4B. LVPECL OUTPUT TERMINATION FIGURE 4A. LVPECL OUTPUT TERMINATION designed to drive 50 Ω transmission lines. Matched imped- ance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 4A and 4B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed cir- cuit and clock component process variations. |
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