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ICS843071AGILF Datasheet(PDF) 8 Page - Integrated Circuit Systems |
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ICS843071AGILF Datasheet(HTML) 8 Page - Integrated Circuit Systems |
8 / 15 page 843071AGI www.icst.com/products/hiperclocks.html REV. A JANUARY 11, 2006 8 Integrated Circuit Systems, Inc. ICS843071I FEMTOCLOCKS™CRYSTAL-TO- LVPECL CLOCK GENERATOR APPLICATION INFORMATION POWER SUPPLY FILTERING TECHNIQUES As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS843071I provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. V CC and VCCA should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 1 illustrates how a 10 Ω resistor along with a 10μF and a .01μF bypass capacitor should be connected to each V CCA pin. FIGURE 1. POWER SUPPLY FILTERING 10 Ω V CCA 10 μF .01 μF 3.3V or 2.5V .01 μF V CC Figure 2. CRYSTAL INPUt INTERFACE CRYSTAL INPUT INTERFACE The ICS843071I has been characterized with 18pF parallel resonant crystals. The capacitor values, C1 and C2, shown in Figure 2 below were determined using an 18pF parallel reso- nant crystal and were chosen to minimize the ppm error. The optimum C1 and C2 values can be slightly adjusted for differ- ent board layouts. ICS84332 XTAL_IN XTAL_OUT X1 18pF Parallel Cry stal C2 22p C1 22p ICS843071I |
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