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ICS84427CMLF Datasheet(PDF) 10 Page - Integrated Circuit Systems |
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ICS84427CMLF Datasheet(HTML) 10 Page - Integrated Circuit Systems |
10 / 13 page 84427CM www.icst.com/products/hiperclocks.html REV. D NOVEMBER 30, 2005 10 Integrated Circuit Systems, Inc. ICS84427 CRYSTAL-TO-LVDS INTEGRATED FREQUENCY SYNTHESIZER/FANOUT BUFFER PRELIMINARY The following component footprints are used in this layout example: All the resistors and capacitors are size 0603. POWER AND GROUNDING Place the decoupling capacitors C3, C5 and C6, as close as possible to the power pins. If space allows, placement of the decoupling capacitor on the component side is preferred. This can reduce unwanted inductance between the decoupling ca- pacitor and the power pin caused by the via. Maximize the power and ground pad sizes and number of vias capacitors. This can reduce the inductance between the power and ground planes and the component power and ground pins. The RC filter consisting of R7, C11, and C16 should be placed as close to the V DDA pin as possible. CLOCK TRACES AND TERMINATION Poor signal integrity can degrade the system performance or cause system failure. In synchronous high-speed digital systems, the clock signal is less tolerant to poor signal integrity than other signals. Any ringing on the rising or falling edge or excessive ring back can cause system failure. The shape of the trace and the trace delay might be restricted by the available space on the board and the component location. While routing the traces, the clock signal traces should be routed first and should be locked prior to routing other signal traces. • The differential 100 Ω output traces should have the same length. • Avoid sharp angles on the clock trace. Sharp angle turns cause the characteristic impedance to change on the transmission lines. • Keep the clock traces on the same layer. Whenever possible, avoid placing vias on the clock traces. Place- ment of vias on the traces can affect the trace charac- teristic impedance and hence degrade signal integ- rity. • To prevent cross talk, avoid routing other signal traces in parallel with the clock traces. If running parallel traces is unavoidable, allow a separation of at least three trace widths between the differential clock trace and the other signal trace. • Make sure no other signal traces are routed between the clock trace pair. • The matching termination resistors should be located as close to the receiver input pins as possible. CRYSTAL The crystal X1 should be located as close as possible to the pins 20 (XTAL_IN) and 19 (XTAL_OUT). The trace length between the X1 and U1 should be kept to a minimum to avoid unwanted parasitic inductance and capacitance. Other signal traces should not be routed near the crystal traces. FIGURE 4B. PCB BOARD LAYOUT FOR ICS84427 VDDA X1 C1 C5 U1 Signals C6 ICS84427 VDD C2 Pin1 C3 VIA C16 C11 50 Ohm Traces R7 GND |
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