Integrated

Circuit

Systems, Inc.

840014AGI

www.icst.com/products/hiperclocks.html

REV. A DECEMBER 23, 2004

9

ICS840014I

PRELIMINARY

The transistor count for ICS840014I is: 3085

θ

JA

VS

θθθθθ

0

200

500

Single-Layer PCB, JEDEC Standard Test Boards

114.5°C/W

98.0°C/W

88.0°C/W

Multi-Layer PCB, JEDEC Standard Test Boards

73.2°C/W

66.6°C/W

63.5°C/W

NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.

Figure 3 shows a schematic example of the ICS840014I. An

example of LVCMOS termination is shown in this schematic.

Additional LVCMOS termination approaches are shown in

the LVCMOS Termination Application Note. In this example,

an 18pF parallel resonant 26.5625MHz crystal is used. The

C1=22pF and C2=22pF are recommended for frequency ac-

curacy. For different board layout, the C1 and C2 may be

slightly adjusted for optimizing frequency accuracy. 1K

Ω

pullup or pulldown resistors can be used for the logic control

input pins.

C1

22pF

Logic Control Input Examples

RU2

Not Install

3.3V

Set Logic

Input to

'1'

3.3V

C4

0.01u

To Logic

Input

pins

C5

0.1u

U1

ICS840014

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

20

19

18

17

F_SEL

nc

nXTAL_SEL

TEST_CLK

OE

MR

nPLL_SEL

VDDA

nc

VDD

XTAL_OUT

XTAL_IN

GND

Q3

Q2

VDDO

nc

GND

Q0

Q1

R4

36

C2

22pF

Zo = 50 Ohm

LVCMOS

3.3V

C6

0.1u

R3

36

VDDA

XTAL_OUT

3.3V

RD1

Not Install

C3

10uF

RU1

1K

RD2

1K

Zo = 50 Ohm

To Logic

Input

pins

LVCMOS

R2

10

3.3V

X1

XTAL_IN

Set Logic

Input to

'0'

ICS80014I