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ICS83947AYI-147 Datasheet(PDF) 7 Page - Integrated Circuit Systems |
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ICS83947AYI-147 Datasheet(HTML) 7 Page - Integrated Circuit Systems |
7 / 10 page 83947AYI-147 http://www.icst.com/products/hiperclocks.html REV. A SEPTEMBER 24, 2004 7 Integrated Circuit Systems, Inc. ICS83947I-147 LOW SKEW, 1-TO-9 LVCMOS/LVTTL FANOUT BUFFER APPLICATION SCHEMATIC EXAMPLE Figure 1 shows an example of ICS83947I-147 application sche- matic. In this example, the device is operated at V CC=3.3V. The decoupling capacitors should be located as close as possible to the power pin. The input is driven by a 3.3V LVCMOS driver. C4 0.1u VCC Zo = 50 Ohm R3 43 R2 43 R1 43 C2 0.1u (U1-22) C3 0.1u C1 0.1u C3 0.1u (U1-10) VDDO (U1-18) C5 0.1u VDDO (U1-14) Zo = 50 U1 ICS83947I-147 1 2 3 4 5 6 7 8 17 18 19 20 21 22 23 24 GND CLK_SEL CLK0 CLK1 CLK_EN OE VDD GND GND VDDO Q5 GND Q4 VDDO Q3 GND VCC VDD=3.3V LVCMOS Zo = 50 Zo = 50 Ohm (U1-27) VDD VDDO=3.3V LVCMOS C2 0.1u (U1-31) R3 43 For the LVCMOS output drivers, only one termination example is shown in this schematic. Additional termination approaches are shown in the LVCMOS Termination Application Note (refer to ICS website). FIGURE 1. ICS83947I-147 SCHEMATIC LAYOUT |
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