Electronic Components Datasheet Search |
|
ICS83840BHLFT Datasheet(PDF) 4 Page - Integrated Circuit Systems |
|
ICS83840BHLFT Datasheet(HTML) 4 Page - Integrated Circuit Systems |
4 / 7 page 83840BH www.icst.com/products/hiperclocks.html REV. A JANUARY 30, 2004 4 Integrated Circuit Systems, Inc. ICS83840B DDR SDRAM MUX t PD V DD 2 V DD 2 PARAMETER MEASUREMENT INFORMATION OUTPUT SKEW 2.5V OUTPUT LOAD AC TEST CIRCUIT V DD = 1.25V ± 0.1V -1.25V ± 0.1V PROPAGATION DELAY tsk(o) V DD 2 V DD 2 nDPx nDPy D or H H or D tsk(o) V DD 2 V DD 2 1.25V 1.25V 1.25V VOH - 0.15V VOL VOH 0V 2.5V tPHZ → tPZH → Output nDPx (See Note) Sn (Low-level enabling) NOTE: The output is high except when disabled by the Sn control. ← 3-STATE OUTPUT ENABLE/DISABLE TIMES BANK SKEW (where X denotes outputs in the same bank) XDP0:XDP9 XDP0:XDP9 SCOPE Qx LVCMOS V DD GND This circuit is used for test purposes only, not intended for application use. |
Similar Part No. - ICS83840BHLFT |
|
Similar Description - ICS83840BHLFT |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.COM |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |