ICS83840BHLFT datasheet(4/7 Pages) ICST

Part #	ICS83840BHLFT

Description	DDR SDRAM MUX

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Manufacturer	ICST [Integrated Circuit Systems]

Direct Link	http://www.icst.com

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4 / 7 page

83840BH

www.icst.com/products/hiperclocks.html

REV. A JANUARY 30, 2004

4

Integrated

Circuit

Systems, Inc.

ICS83840B

DDR SDRAM MUX

t

PD

V

DD

2

V

DD

2

PARAMETER MEASUREMENT INFORMATION

OUTPUT SKEW

2.5V OUTPUT LOAD AC TEST CIRCUIT

V

DD = 1.25V ± 0.1V

-1.25V ± 0.1V

PROPAGATION DELAY

tsk(o)

V

DD

2

V

DD

2

nDPx

nDPy

D or H

H or D

tsk(o)

V

DD

2

V

DD

2

1.25V

VOH - 0.15V

VOL

VOH

0V

2.5V

tPHZ →

tPZH →

Output nDPx

(See Note)

Sn

(Low-level

enabling)

NOTE: The output is high except when disabled by the Sn control.

←

3-STATE OUTPUT ENABLE/DISABLE TIMES

BANK SKEW (where X denotes outputs in the same bank)

XDP0:XDP9

SCOPE

Qx

LVCMOS

V

DD

GND

This circuit is used for test purposes only,

not intended for application use.

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