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ICS8432BY51L Datasheet(PDF) 9 Page - Integrated Circuit Systems |
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ICS8432BY51L Datasheet(HTML) 9 Page - Integrated Circuit Systems |
9 / 17 page 8432BY-51 www.icst.com/products/hiperclocks.html REV. C APRIL 8, 2005 9 Integrated Circuit Systems, Inc. ICS8432-51 700MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER Figure 3. CRYSTAL INPUt INTERFACE V CC - 2V 50 Ω 50 Ω RTT Z o = 50Ω Z o = 50Ω FOUT FIN RTT = Z o 1 ((V OH + VOL) / (VCC – 2)) – 2 3.3V 125 Ω 125 Ω 84 Ω 84 Ω Z o = 50Ω Z o = 50Ω FOUT FIN The clock layout topology shown below is a typical termina- tion for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUTx and nFOUTx are low impedance follower outputs that generate ECL/LVPECL compatible outputs.Therefore, terminat- ing resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to FIGURE 4B. LVPECL OUTPUT TERMINATION FIGURE 4A. LVPECL OUTPUT TERMINATION drive 50 Ω transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 4A and 4B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. TERMINATION FOR LVPECL OUTPUTS CRYSTAL INPUT INTERFACE The ICS8432-51 has been characterized with 18pF parallel reso- nant crystals. The capacitor values, C1 and C2, shown in Fig- ure 3 below were determined using a 25MHz, 18pF parallel reso- nant crystal and were chosen to minimize the ppm error. The optimum C1 and C2 values can be slightly adjusted for different board layouts. C1 22p X1 18pF Parallel Cry stal C2 22p XTAL2 XTAL1 |
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