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ICS650-36 Datasheet(PDF) 1 Page - Integrated Circuit Systems |
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ICS650-36 Datasheet(HTML) 1 Page - Integrated Circuit Systems |
1 / 7 page ICS650-36 MDS 650-36 D 1 Revision 030206 Integrat ed Circuit Sy stems ● 5 25 Race Street, San Jose, CA 9 5126 ● tel (408 ) 2 97-12 01 ● www.icst.co m Networking & PCI Clock Source Description The ICS650-36 is a low cost frequency generator designed to support networking and PCI applications. Using analog/digital Phase Locked-Loop (PLL) techniques, the device uses a standard fundamental mode, inexpensive crystal input of 25 MHz to produce four output clocks supporting LAN, PCI, and 100M SDRAM functions. The device also has a power down feature that tri-states the clock outputs and turns off the PLL when the PDTS pin is taken low. Features • Packaged in 16-pin TSSOP • Available in Pb (lead) free package • Replaces multiple crystals and oscillators • Input crystal or clock frequency of 25 MHz • Fixed reference output frequency of 25 MHz • Selectable output frequencies of 33.3, 33.333, 50, 66.666, 100, and 125 MHz • Duty cycle of 40/60 • Operating voltage of 3.3 V • Advanced, low-power CMOS process • Industrial and commercial temperature ranges Block Diagram X1/ICLK X2 PLL1 PLL2 Crystal Oscillator/ Clock Buffer 25 MHz crystal input External capacitors may be required. VDD GND PDTS (all outputs and PLLs) CLK1 3 3 PLL3 CLK3 CLK2 REF Select/ Control Circuit 3 S2:0 |
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