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ICS613MLF Datasheet(PDF) 1 Page - Integrated Circuit Systems |
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ICS613MLF Datasheet(HTML) 1 Page - Integrated Circuit Systems |
1 / 6 page MDS 613 C 1 Revision 111204 Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com LOW PHASE NOISE CLOCK MULTIPLIER ICS613 Description The ICS613 is a low cost, low phase noise, high performance clock synthesizer for any applications that require low phase noise and low jitter. It is ICS’ lowest phase noise multiplier. Using ICS’ patented analog and digital Phase Locked Loop (PLL) techniques, the chip can accept a 25MHz crystal or clock input, and produces output clocks up to 157.5 MHz. The chip has separate power supplies for the clock outputs, allowing each output to be run at different voltages. It also allows the core of the chip to operate at 3.3V, while the output clocks run at either 2.5V or 3.3V. Features • Packaged in 16 pin SOIC • Available in Pb (lead) free package • Uses a fundamental 25MHz crystal or clock • Operating voltage of 3.3 V • Separate output voltage supplies which can run at 2.5 V or 3.3 V • Output clocks up to 157.5 MHz • Low phase noise: -110 dBc/Hz at 10 kHz • Low jitter of 36 ps (one sigma) • Advanced, low power, sub-micron CMOS process Block Diagram GND 5 Reference Divider Phase Comparator, Charge Pump, and Loop Filter VCO VCO Divider Output Divider S2:SO X1/ICLK X2 Crystal or clock input Capacitors must be used with a crystal input Crystal Oscillator VDDO1 VDD 2 CLK1 CLK2 VDDO2 3 |
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