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ICS527-04 Datasheet(PDF) 2 Page - Integrated Circuit Systems |
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ICS527-04 Datasheet(HTML) 2 Page - Integrated Circuit Systems |
2 / 9 page Clock Slicer User Configurable PECL input Zero Delay Buffer MDS 527-04 D 2 Revision 122804 Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com ICS527-04 Pin Assignment 28-pin (150 mil) SSOP Output Frequency and Output Divider Table IRANGE Setting Table Pin Descriptions 18 7 17 8 16 9 15 F B PEC L 10 F B PEC L 11 GN D 12 PE C L O 13 PEC L I N 14 PEC L I N GN D RE S F6 F0 F5 F3 F1 F4 22 21 20 19 F2 PE C L O 5 6 S1 VD D VD D 24 23 R0 3 4 IR A N G E S0 R1 26 25 R2 1 2 R5 R6 R3 28 27 R4 S1 Pin 5 S0 Pin 4 Output Frequency (MHz) PECLO Output Pair 00 10 - 80 0 1 5 - 40 1 0 2.5 - 20 1 1 20 -160 IRANGE Criteria 0 if (FBPECL < 80 MHz) and (PECLIN < 80 MHz) 1 if (FBPECL > 80 MHz) or (PECLIN > 80 MHz) Pin Number Pin Name Pin Type Pin Description 1 - 2 24 - 28 R5, R6, R0-R4 Input Reference divider word input pins determined by user. Forms a binary number from 0 to 127. Internal pull-up. 3 IRANGE Input Set for proper frequency range of input clocks. See table above. 4 - 5 S0, S1 Input Select pins for output frequency range. See table above. Internal pull-up. 6, 23 VDD Power Connect to +3.3 V. 7 FBPECL Input PECL feedback input to PLL. 8 FBPECL Input PECL feedback input to PLL. 9, 20 GND Power Connect to ground 10 PECLIN Input PECL input clock. 11 PECLIN Input Complementary PECL input clock. 12 - 18 F0-F6 Input Feedback divider word input pins determined by user. Forms a binary number from 0 to 127. Internal pull-up 19 RES BIAS Resistor connection to VDD for setting level of PECL outputs. 21 PECLO Output Complementary PECL output. 22 PECLO Output PECL output. Rising edge aligns with PECLIN when connected directly to FBPECL. |
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