V3025SO28A datasheet(10/17 Pages) EMMICRO

Part #	V3025SO28A

Description	17Very Low Power 8-Bit 32 kHz RTC Module with Digital Trimming, User RAM and Battery Switch-over

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Manufacturer	EMMICRO [EM Microelectronic - MARIN SA]

Direct Link	http://www.emmicroelectronic.com

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V3025

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Pin Description

SO28 Package

Name

Description

1

SYNC

Time synchronization

I

2

PFI

Power fail

I

3

AD0

Bit 0 from MUX address /

data bus

I/O

4

AD1

Bit 1 from MUX address /

data bus

I/O

5

AD2

Bit 2 from MUX address /

data bus

I/O

6

AD3

Bit 3 from MUX address /

data bus

I/O

7

A

/D

Address / data decode

I

8

IRQ

Interrupt request

O

9

VOUT

Switch-over output

O

10-14

VSS

Supply ground (substrate)

GND

15-19

VDD

Positive supply terminal

PWR

20

PFO

Power fail output

O

21

CS

Chip select

I

22

WR

(Intel) or R/ W

(Motorola)

I

23

RD

(Intel) or DS (Motorola)

I

24

AD4

Bit 4 from MUX address /

data bus

I/O

25

AD5

Bit 5 from MUX address /

data bus

I/O

26

AD6

Bit 6 from MUX address /

data bus

I/O

27

AD7

Bit 7 from MUX address /

data bus

I/O

28

VBAT

Battery supply

PWR

Table 5

Functional Description

Power Supply, Data Retention and Standby

The V3025 is put in standby mode by activating the PFI

input. When pulled logic low, PFI will disable the input

lines, and immediately take to high impedance the lines

AD 0-7. Input states must be under control whenever

PFI

is deactivated. If no specific power fail signal can be

provided, PFI can be tied to the system RESET . Even

in standby the interrupt request pin IRQ will pull to ground

upon an unmasked alarm interrupt occurring.

Switch-over

The switch-over supplies the core of the RTC. The I/O

pads are supplied by VDD, except for IRQ and SYNC .

The SYNC input is internally pulled-up to VOUT, IRQ can

be externally pulled-up between 2 and 5.5V. The switch-

over circuitry works in recovery mode. During switching,

both transistors (VDD to VOUT and VBAT to VOUT) are ON.

This is to guarantee that the RTC is always supplied. The

power fail signal becomes active ( PFO = 0) when VDD <

VBAT (see Table 4).

Initialisation

When power is first applied to the V3025 all registers have

a random value.

To initialise the V3025, software must first write a 1 to the

initialisation bit (addr. 2 bit 4) and then a 0. This sets the

Frequency Tuning bit and clears all other status bits.

The time and date parameters should then be loaded into

the RAM (addr. 20 to 28 hex) and then transferred to the

reserved clock area using the clock command followed by

a write.

The digital trimming register must then be initialised

by writing 210 (D2 hex) to it, if Frequency Tuning is

not required.

After having written a value to the

digital trimming register the frequency tuning mode

bit can be cleared.

RAM Configuration

The RAM area of the V3025 has a reserved clock and

time area, a data space, user RAM and an address

command space (see Table 10 or Fig. 10). The reserved

clock and timer area is not directly accessible to the user,

it is used for internal time keeping and contains the

current time and date plus the timer parameters.

Data Space

All locations in the data space are Read/Write. The data

space is directly accessible to the user and is divided into

five areas:

Status Registers

– three registers used for status and

control data for the device (see Table 7, 8 and 9).

Reserved bits must be set to 0.

Digital Trimming Register

– a special function described

under "Frequency Tuning".

Time and Date Registers

– 9 time and date locations

which are loaded with, either the current time and date

parameters from the reserved clock area or the time and

date parameters to be transferred to the reserved clock

area.

Alarm Registers

– 5 locations used for setting the alarm

parameters.

Timer Registers

– 4 locations which are loaded with

either the timer parameters from the reserved timer area

or the timer parameters to be transferred to the reserved

timer area.

User RAM

The V3025 has 16 bytes of general purpose RAM

available for the users applications. This RAM block is

located at addresses 50 to 5F hex and is maintained even

in the standby mode ( PFI active). The commands, or the

time set lock bit, have no effect on the user RAM block.

Reading or writing to the user RAM is similar to reading or

writing to any system RAM address.

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V3025SO28A Datasheet(PDF) 10 Page - EM Microelectronic - MARIN SA

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