PRELIMINARY
CYP15G0403DXB
CYV15G0403DXB
Document #: 38-02065 Rev. *C
Page 9 of 43
LDTDEN
LVTTL Input,
internal pull-up
Level Detect Transition Density Enable. When LDTDEN is HIGH, the Signal
Level Detector, Range Controller, and Transition Density Detector are all enabled
to determine if the RXPLL tracks REFCLKx
± or the selected input serial data
stream. If the Signal Level Detector, Range Controller, or Transition Density
Detector are out of their respective limits while LDTDEN is HIGH, the RXPLL locks
to REFCLK
± until such a time they become valid. The (SDASEL[A..D][1:0]) are
used to configure the trip level of the Signal Level Detector. The Transition Density
Detector limit is one transition in every 60 consecutive bits. When LDTDEN is
LOW, only the Range Controller is used to determine if the RXPLL tracks
REFCLKx
± or the selected input serial data stream. For the cases when
RXCKSELx = 0 (recovered clock), it is recommended to set LDTDEN = HIGH.
ULCA
ULCB
ULCC
ULCD
LVTTL Input,
internal pull-up
Use Local Clock. When ULCx is LOW, the RXPLL is forced to lock to REFCLKx
±
instead of the received serial data stream. While ULCx is LOW, the LFIx for the
associated channel is LOW indicating a link fault.
When ULCx is HIGH, the RXPLL performs Clock and Data Recovery functions on
the input data streams. This function is used in applications in which a stable
RXCLKx
± is needed. In cases when there is an absence of valid data transitions
for a long period of time, or the high-gain differential serial inputs (INx
±) are left
floating, there may be brief frequency excursions of the RXCLKx
± outputs from
REFCLKx
±.
SPDSELA
SPDSELB
SPDSELC
SPDSELD
3-Level Select[4]
static control input
Serial Rate Select. The SPDSELx inputs specify the operating signaling-rate
range of each channel
’s transmit and receive PLL.
LOW = 195
– 400 MBd
MID = 400
– 800 MBd
HIGH = 800
– 1500 MBd.
INSELA
INSELB
INSELC
INSELD
LVTTL Input,
asynchronous
Receive Input Selector. The INSELx input determines which external serial bit
stream is passed to the receiver
’s Clock and Data Recovery circuit. When INSELx
is HIGH, the Primary Differential Serial Data Input, INx1
±, is selected for the
associated receive channel. When INSELx is LOW, the Secondary Differential
Serial Data Input, INx2
±, is selected for the associated receive channel.
LPENA
LPENB
LPENC
LPEND
LVTTL Input,
asynchronous,
internal pull-down
Loop-Back-Enable. The LPENx input enables the internal serial loop-back for the
associated channel. When LPENx is HIGH, the transmit serial data from the
associated channel is internally routed to the associated receive Clock and Data
Recovery (CDR) circuit. All enabled serial drivers on the channel are forced to
differential logic-1, and the serial data inputs are ignored. When LPENx is LOW,
the internal serial loop-back function is disabled.
LFIA
LFIB
LFIC
LFID
LVTTL Output,
asynchronous
Link Fault Indication Output. LFIx is an output status indicator signal. LFIx is the
logical OR of six internal conditions. LFIx is asserted LOW when any of the
following conditions is true:
• Received serial data rate outside expected range
• Analog amplitude below expected levels
• Transition density lower than expected
• Receive channel disabled
• ULCx is LOW
• Absence of REFCLKx±.
Device Configuration and Control Bus Signals
WREN
LVTTL input,
asynchronous,
internal pull-up
Control Write Enable. The WREN input writes the values of the DATA[7:0] bus
into the latch specified by the address location on the ADDR[3:0] bus.[5]
Notes:
4.
3-Level Select inputs are used for static configuration. These are ternary inputs that make use of logic levels of LOW, MID, and HIGH. The LOW level is usually
implemented by direct connection to VSS (ground). The HIGH level is usually implemented by direct connection to VCC (power). The MID level is usually
implemented by not connecting the input (left floating), which allows it to self bias to the proper level.
5.
See Device Configuration and Control Interface for detailed information on the operation of the Configuration Interface.
Pin Definitions (continued)
CYP(V)15G0403DXB Quad HOTLink II Transceiver
Name
I/O Characteristics
Signal Description
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