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ICS525R-11LF Datasheet(PDF) 2 Page - Integrated Circuit Systems |
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ICS525R-11LF Datasheet(HTML) 2 Page - Integrated Circuit Systems |
2 / 9 page User Configurable Clock MDS 525-01/02/11/12 Q 2 Revision 101105 Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com ICS525-01/02/11/12 Pin Assignment Pin Descriptions KEY: I(PU) = Input with internal pull-up resistor; X1, X2 = crystal connections 18 7 17 8 16 9 15 X1/ICLK 10 X2 11 GND 12 CLK 13 V0 14 V1 GND PD V8 V2 V7 V5 V3 V6 22 21 20 19 V4 REF 5 6 S2 VDD VDD 24 23 R0 3 4 S0 S1 R1 26 25 R2 1 2 R5 R6 R3 28 27 R4 ICS525-01/-02/-11/-12 Pin Number Pin Name Pin Type Pin Description 1, 2, 24-28 R5, R6, R0-R4 I(PU) Reference divider word input pins determined by user. Forms a binary number from 0 to 127. 3, 4, 5 S0, S1, S2 I(PU) Select pins for output divider determined by user. See table on page 3 6, 23 VDD Power Connect to VDD. 7 X1/ICLK X1 Crystal connection. Connect to a parallel resonant fundamental crystal or input clock. 8 X2 X2 Crystal connection. Connect to a crystal or leave unconnected for clock. 9, 20 GND Power Connect to ground. 10 - 18 V0 - V8 I(PU) VCO divider word input pins determined by user. Forms a binary number from 0 to 511. 19 PD Input Power-down. Active low. Turns off entire chip when low. Clock outputs stop low. 21 CLK Output Output clock determined by status of R0-R6, V-V8, S0-S2, and input frequency. 22 REF Output Reference output. Buffered crystal oscillator (or clock ) output. |
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