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ICS525-01RIT Datasheet(PDF) 1 Page - Integrated Circuit Systems |
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ICS525-01RIT Datasheet(HTML) 1 Page - Integrated Circuit Systems |
1 / 9 page ICS525-01/02/11/12 MDS 525-01/02/11/12 Q 1 Revision 101105 Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com User Configurable Clock Description The ICS525-01/02/11/12 are the most flexible way to generate a high-quality, high-accuracy, high-frequency clock output from an inexpensive crystal or clock input. The user can configure the device to produce nearly any output frequency from any input frequency by grounding or floating the select pins. Neither microcontroller, software, nor device programmer are needed to set the frequency. Using Phase-Locked Loop (PLL) techniques, the device accepts a standard fundamental mode, inexpensive crystal to produce output clocks up to 250 MHz. It can also produce a highly accurate output clock from a given input clock, keeping them frequency locked together. For similar capability with a serial interface, use the ICS307. For simple multipliers to produce common frequencies, refer to the ICS50x family of parts, which are smaller and more cost effective. These products are intended for clock generation. They have low output jitter (variation in the output period), but input to output skew and jitter are not defined nor guaranteed. For applications which require defined input to output timing, use the ICS527-01. Features • Packaged as 28-pin SSOP (150 mil body) • Industrial and commercial versions available in Pb (lead) free package • User determines the output frequency by setting all internal dividers • Eliminates need for custom oscillators • No software needed • Online calculator determines register settings • Pull-ups on all select inputs • Input crystal frequency of 5 - 27 MHz • Input clock frequency of 2 - 50 MHz • Very low jitter • Duty cycle of 45/55 up to 200 MHz • Operating voltage of 3.0 V or 5.5 V • Ideal for oscillator replacement • Industrial temperature version available • For Zero Delay, refer to the ICS527 Block Diagram VDD GND 2 2 CLK REF Reference Divider Phase Comparator, Charge Pump, and Loop Filter VCO VCO Divider Output Divider 9 73 R6:R0 V8:V0 S2:S0 X1/ICLK X2 Crystal or clock input Optional crystal capacitors Crystal Oscillator PD |
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