Clock Slicer User Configurable PECL Input Zero Delay Buffer

MDS 527-02 F

2

Revision 022806

Integrated Circuit Systems, Inc.

ICS527-02

Pin Assignment

28-pin 150 mil body SSOP

Output Frequency Range Table

CLK2 Operation Table

Pin Descriptions

18

7

17

8

16

9

15

PE C L IN

10

PE C L IN

11

GN D

12

CL K 2

13

OE C L K 2

14

F0

GN D

PDTS

FB IN

F1

F6

F4

F2

F5

22

21

20

19

F3

CL K 1

5

6

S1

VD D

VDD

24

23

R0

3

4

DIV 2

S0

R1

26

25

R2

1

2

R5

R6

R3

28

27

R4

S1 S0

Output Frequency (MHz)

Commercial

Industrial

0

0

10 - 50

16 - 45

0

1

5 - 40

8 - 33

1

0

4 - 10

4 - 8

1

1

20 -160

32 - 140

OECLK2

DIV2

CLK2

0X

Z

1

0

SYNC

11

CLK1/2

Pin

Number

Pin

Name

Pin

Type

Pin Description

1,2, 24-28

R5, R6,

R0-R4

Input

Reference divider word input pins determined by user. Forms a binary number

from 0 to 127. Internal pull-up.

3

DIV2

Input

Selects CLK2 function to output a SYNC signal or a divide by 2 of CLK1 based

on the table above. Internal pull-up.

4, 5

S0, S1

Input

Select pins for output divider determined by user. See table above. Internal

pull-up.

6, 23

VDD

Power

Connect to +3.3 V.

7

PECLIN

Input

True PECL input clock.

8

PECLIN

Input

Complementary PECL input clock.

9, 20

GND

Power

Connect to ground

10

OECLK2

Input

CLK2 Output Enable. CLK2 tri-stated when low. Internal pull-up.

11-17

F0-F6

Input

Feedback divider word input pins determined by user. Forms a binary number

from 0 to 127. Internal pull-up

18

FBIN

Input

Feedback clock input

19

PDTS

Input

Power Down. Active low. Turns off entire chip when low, both clock outputs are

tri-stated. Internal pull-up.

21

CLK2

Output

Output clock 2. Can be SYNC pulse or a low skew divide by 2 of CLK1.

22

CLK1

Output

Output clock 1.