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ICS487G-25LFT Datasheet(PDF) 2 Page - Integrated Circuit Systems |
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ICS487G-25LFT Datasheet(HTML) 2 Page - Integrated Circuit Systems |
2 / 6 page Quad PLL for DTV MDS 487-25 A 2 Revision 050604 Integrated Circuit Systems l 525 Race Street, San Jose, CA 95126 l tel (408) 297-1201 l www.icst.com ICS487-25 Pin Assignment ACLK Output Selection Table Note: When S1 and S0 are switched, all other output clocks will remain stable throughout the transition. Pin Descriptions 12 1 11 2 10 3 9 X1/ICLK 4 S0 5 S1 6 VDD 7 48M 8 VDD PDTS GND VDD GND GND ACLK 20M 33.0M 16 15 14 13 24.576M X2 16 pin (173 mil) TSSOP S1 S0 ACLK (MHz) 0 0 18.432 0 1 16.9344 1 0 12.288 1 1 18.432 Pin Number Pin Name Pin Type Pin Description 1 X1/ICLK Input Crystal connection. Connect to 27 MHz crystal or clock input. 2 S0 Input Select pin 0. Determines ACLK output frequency per table above. Internal pull up resistor. 3 S1 Input Select pin 1. Determines ACLK output frequency per table above. Internal pull up resistor. 4 48M Output 48 MHz clcok output. Weak internal pull-down when tri-state. 5 VDD Power Connect to +3.3 V. 6 GND Power Connect to ground. 7 20M Output 20 MHz clock output. Weak internal pull-down when tri-state. 8 24.576M Output 24.576 MHz clock output. Weak internal pull-down when tri-state. 9 ACLK Output Audio clock output. Determined by table above. Weak internal pull-down when tri-state 10 33.0M Output 33.0 MHz clock output. Weak internal pull-down when tri-state. 11 GND Power Connect to ground. 12 VDD Power Connect to +3.3 V. 13 GND Power Connect to ground. 14 PDTS Input Powers down entire chip and tri-states outputs when low. Internal pull-up resistor. 15 VDD Power Connect to +3.3 V. 16 X2 Input Connect to 27 MHz crystal or float for clock input. |
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