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ICS487G-25T Datasheet(PDF) 1 Page - Integrated Circuit Systems |
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ICS487G-25T Datasheet(HTML) 1 Page - Integrated Circuit Systems |
1 / 6 page ICS487-25 MDS 487-25 A 1 Revision 050604 Integrated Circuit Systems l 525 Race Street, San Jose, CA 95126 l tel (408) 297-1201 l www.icst.com Quad PLL for DTV Description The ICS487-25 generates five high-quality, high-frequency clock outputs. It is designed to replace crystals and crystal oscillators in DTV applications. Using ICS’ patented Phase Locked Loop (PLL) techniques, the device runs from a lower frequency crystal or clock input. Because there is zero ppm frequency synthesis error on the audio clocks, the audio will remain locked to the video. Features • Packaged in 16-pin TSSOP • Available in Pb-free packaging • Replaces multiple crystals and oscillators • Input crystal or clock frequency of 27 MHz • Zero ppm frequency synthesis error • Duty cycle of 45/55 • Operating voltage of 3.3 V • Advanced, low power CMOS process Block Diagram X1/ICLK X2 PLL1 PLL2 Crystal Oscillator/ Clock Buffer 27 MHz clock or crystal input External capacitors may be required. VDD GND PDTS (all outputs and PLLs) 20M ACLK 3 3 PLL3 33.0M PLL4 24.576M S1:0 2 48M |
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