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ICS307M-02ILF Datasheet(PDF) 4 Page - Integrated Circuit Systems |
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ICS307M-02ILF Datasheet(HTML) 4 Page - Integrated Circuit Systems |
4 / 9 page SERIALLY PROGRAMMABLE CLOCK SOURCE MDS 307-01/02 F 4 Revision 121304 In te gr ated Circuit Systems ● 525 Ra ce Street, San Jose, CA 9512 6 ● tel (4 08) 297 -1 201 ● www.icst.com ICS307-01/02 Setting the Device Characteristics The tables below show the settings which can be configured, as well as the VCO and Reference dividers. Table 1. Output Divide and Maximum Output Frequency Table 2. CLK2 Output Table 3. Output Duty Cycle Configuration Note: The TTL bit optimizes the duty cycle at different VDD. When VDD is 5 V, set to 0 for a near-50% duty cycle with TTL levels. When VDD is 3.3 V, set this bit to 1 so the 50% duty cycle is achieved at VDD/2. Table 4. Crystal Load Capacitance Note: f is the crystal frequency in MHz between 10 and 27 MHz. Effective load capacitance will be higher for crystal frequencies lower than 10 MHz. If a clock input is used, set C1 = 0 and C0 = 0. S2 S1 S0 CLK1 Output Divide Max. Frequency 5 V or 3.3 V (MHz) Max. Frequency Industrial Temp. Version 00 010 40 36 00 1 2 200 180 01 08 50 45 01 14 100 90 10 05 80 72 10 17 55 50 11 0 3 135 120 11 1 6 67 60 F1 F0 CLK2 00 REF 01 FREF/2 10 OFF (Low) 11 FCLK1/2 TTL Duty Cycle Measured At Recommended VDD 0 1.4 V 5 V 1 VDD/2 3.3 V C1 C0 VDD = 5V VDD = 3.3V 0 0 22.3 - 0.083 f 22.1 - 0.094 f 0 1 23.1 - 0.093 f 22.9 - 0.108 f 1 0 23.7 - 0.106 f 23.5 - 0.120 f 1 1 24.4 - 0.120 f 24.2 - 0.135 f |
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