PLL602-38N

4x Low Phase Noise Multiplier PECL XO

Universal Low Phase Noise IC

47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 11/24/04 Page 1

FEATURES

• Low phase noise output (-127dBc @ 10kHz fre-

quency offset).

• 12MHz to 25MHz crystal input.

• 48MHz to 100MHz PECL output.

• 3.3V operation.

• Available in Green (RoHS Compliant) 8-Pin

SOIC package.

DESCRIPTION

The PLL602-38N is a high performance and low

phase noise PECL XO IC chip. It provides phase

noise performance as low as –127dBc at 10kHz off-

set and a typical RMS jitter of 4.5pS RMS ( at

100MHz ). It accepts a fundamental parallel reso-

nant mode crystal input from 12MHz to 25MHz.

BLOCK DIAGRAM

PIN CONFIGURATION

(Top View)

X1

X2

GND

GND

VDD

CLKB

VDD

CLK

4

3

2

1

8

7

6

5

Q

PLL602-38N

Q

PLL

(Phase

Locked

Loop)

Oscillator

Amplifier

XIN

XOUT