®

AS4C256K16FO

4/11/01; V.0.9.1

Alliance Semiconductor

P. 2 of 25

Functional description

The AS4C256K16FO is a high-performance 4 megabit CMOS Dynamic Random Access Memory (DRAM) device organized as

262,144 words × 16 bits. The AS4C256K16FO is fabricated with advanced CMOS technology and designed with innovative

design techniques resulting in high speed, extremely low power and wide operating margins at component and system levels.

The AS4C256K16FO features a high-speed page mode operation in which high speed read, write and read-write are performed

on any of the 512

× 16 bits defined by the column address. The asynchronous column address uses an extremely short row

address capture time to ease the system-level timing constraints associated with multiplexed addressing. Output is tri-stated by a

column address strobe (CAS) which acts as an output enable independent of RAS. Very fast CAS to output access time eases

system design.

Refresh on the 512 address combinations of A0–A8 during an 8 ms period is accomplished by performing any of the following:

•RAS-only refresh cycles

• Hidden refresh cycles

•CAS-before-RAS refresh cycles

• Normal read or write cycles

The AS4C256K16FO is available in standard 40-pin plastic SOJ and 44-pin TSOP II packages compatible with widely available

automated testing and insertion equipment. System level features include single power supply of 5V ± 10% tolerance and direct

interface with TTL logic families.

Logic block diagram

Recommended operating conditions

* Self-refresh option is available for new generation device only. Contact Alliance for more information.

Parameter

Symbol

Min

Typ

Max

Unit

Supply voltage

4.5

5.0

5.5

V

GND

0.0

0.0

0.0

V

Input voltage

2.4

–

V

–1.0

–

0.8

V

512

×512×16

array

(4,194,304)

Sense amp

A0

A1

A2

A3

A4

A5

A6

A7

GND

A8

Column decoder

OE

RAS

UCAS

WE

LCAS

I/O0 to I/O15

Substrate

bias generator

Data

I/O

buffer

RAS clock

generator

CAS clock

generator

WE clock

generator