10
P/N: PM0440
REV. 1.6, JUL. 16, 1998
MX29F1611
bytes(64 words)boundary. The page address must be
valid during each high to low transition of WE or CE. A-1
to A5 specify the byte address within the page, A0 to A5
specify the word address withih the page. The byte(word)
may be loaded in any order; sequential loading is not
required. If a high to low transition of CE or WE is not
detected whithin 100us of the last low to high transition,
the load period will end and the internal programming
period will start. The Auto page program terminates when
status on DQ7 is '1' at which time the device stays at read
status register mode until the CIR contents are altered by
a valid command sequence.(Refer to table 3,6 and Figure
1,7,8)
Sector erase is a six-bus cycle operation. There are two
"unlock" write cycles. These are followed by writing the
set-up command-80H. Two more "unlock" write cycles
are then followed by the sector erase command-30H.
The sector address is latched on the falling edge of WE,
while the command (data) is latched on the rising edge of
WE.
Sector erase does not require the user to program the
device prior to erase. The system is not required to
provide any controls or timings during these operations.
The automatic sector erase begins on the rising edge of
the last WE pulse in the command sequence and
terminates when the status on DQ7 is "1" at which time
the device stays at read status register mode. The device
remains enabled for read status register mode until the
CIR contents are altered by a valid command
sequence.(Refer to table 3,6 and Figure 3,4,7,9))
SECTOR ERASE
ERASE SUSPEND
This command only has meaning while the the WSM is
executing
SECTOR or CHIP erase operation, and
therefore will only be responded to during SECTOR or
CHIP erase operation. After this command has been
executed, the CIR will initiate the WSM to suspend erase
operations, and then return to Read Status Register
mode. The WSM will set the DQ6 bit to a "1". Once the
WSM has reached the Suspend state,the WSM will set
the DQ7 bit to a "1", At this time, WSM allows the CIR to
respond to the Read Array, Read Status Register, Abort
and Erase Resume commands only. In this mode, the
CIR will not resopnd to any other comands. The WSM will
continue to run, idling in the SUSPEND state, regardless
of the state of all input control pins.
A19
A18
A17
A16
Address Range[A19, -1]
SA0
0
0
0
0
000000H--01FFFFH
SA1
0
0
0
1
020000H--03FFFFH
SA2
0
0
1
0
040000H--05FFFFH
SA3
0
0
1
1
060000H--07FFFFH
SA4
0
1
0
0
080000H--09FFFFH
...
....
...
...
................
SA15
1
1
1
1
1E0000H--1FFFFFH
Table 5. MX29F1611 Sector Address Table
(Byte-Wide Mode)
CHIP ERASE
Chip erase is a six-bus cycle operation. There are two
"unlock" write cycles. These are followed by writing the
"set-up" command-80H. Two more "unlock" write cycles
are then followed by the chip erase command-10H.
Chip erase does not require the user to program the
device prior to erase.
The automatic erase begins on the rising edge of the last
WE pulse in the command sequence and terminates
when the status on DQ7 is "1" at which time the device
stays at read status register mode. The device remains
enabled for read status register mode until the CIR
contents
are
altered
by
a
valid
command
sequence.(Refer to table 3,6 and Figure 2,7,9)
ERASE RESUME
This command will cause the CIR to clear the suspend
state and set the DQ6 to a '0', but only if an Erase
Suspend command was previously issued.
Erase
Resume will not have any effect in all other conditions.
INDEX
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