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TMS417400A Datasheet(PDF) 6 Page - Texas Instruments |
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TMS417400A Datasheet(HTML) 6 Page - Texas Instruments |
6 / 27 page TMS416400A, TMS417400A 4194304 BY 4-BIT DYNAMIC RANDOM-ACCESS MEMORIES SMKS889B – AUGUST 1996 – REVISED OCTOBER 1997 6 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 RAS-only refresh TMS416400A A refresh operation must be performed at least once every 64 ms to retain data. This can be achieved by strobing each of the 4 096 rows (A0 – A11). A normal read- or write cycle refreshes all bits in each row that is selected. A RAS-only operation can be used by holding CAS at the high (inactive) level, conserving power as the output buffers remain in the high-impedance state. Externally generated addresses must be used for a RAS-only refresh. TMS417400A A refresh operation must be performed at least once every 32 ms to retain data. This can be achieved by strobing each of the 2 048 rows (A0 – A10). A normal read- or write cycle refreshes all bits in each row that is selected. A RAS-only operation can be used by holding CAS at the high (inactive) level, conserving power as the output buffers remain in the high-impedance state. Externally generated addresses must be used for a RAS-only refresh. hidden refresh Hidden refresh can be performed while maintaining valid data at the output pin. This is accomplished by holding CAS at VIL after a read operation and cycling RAS after a specified precharge period, similar to a RAS-only refresh cycle. The external address is ignored, and the refresh address is generated internally. CAS-before-RAS ( CBR ) refresh CBR refresh is utilized by bringing CAS low earlier than RAS (see parameter tCSR) and holding it low after RAS falls (see parameter tCHR). For successive CBR refresh cycles, CAS can remain low while cycling RAS. The external address is ignored, and the refresh address is generated internally. power up To achieve proper device operation, an initial pause of 200 µs, followed by a minimum of eight initialization cycles, is required after power up to the full VCC level. These eight initialization cycles must include at least one refresh ( RAS-only or CBR ) cycle. test mode The test mode is initiated with a CBR-refresh cycle while simultaneously holding the W input low. The entry cycle performs an internal-refresh cycle while internally setting the device to perform a parallel read or write on subsequent cycles. While in the test mode, any data sequence can be performed. The device exits test mode if a CBR-refresh cycle (with W held high) or a RAS-only refresh cycle is performed. In the test mode, the device is configured as 1 024K bits × 4 bits for each DQ. Each DQ pin has a separate 4-bit parallel-read- and write data bus that ignores column addresses A0 and A1. During a read cycle, the four internal bits are compared for each DQ pin separately. If the four bits agree, DQ goes high; if not, DQ goes low. Test time is reduced by a factor of four for this series of events. |
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