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PLL502-39 Datasheet(PDF) 5 Page - PhaseLink Corporation |
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PLL502-39 Datasheet(HTML) 5 Page - PhaseLink Corporation |
5 / 9 page PLL502-35/-37/-38/-39 750kHz – 800MHz Low Phase Noise Multiplier VCXO Universal Low Phase Noise IC’s 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 01/19/06 Page 5 5. Jitter Specifications PARAMETERS CONDITIONS FREQUENCY MIN. TYP. MAX. UNITS 19.44MHz 2.2 77.76MHz 4.5 155.52MHz 4.5 Period jitter RMS With capacitive decoupling be- tween VDD and GND. Over 10,000 cycles. 622.08MHz 5.0 ps 19.44MHz 17 77.76MHz 25 155.52MHz 27 Period jitter Peak-to- Peak1 With capacitive decoupling be- tween VDD and GND. Over 10,000 cycles. 622.08MHz 35 ps 155.52MHz 2.5 4 Integrated jitter RMS2 Integrated 12 kHz to 20 MHz 622.08MHz 2.5 4 ps 6. Phase Noise Specifications PARAMETERS FREQUENCY @10Hz @100Hz @1kHz @10kHz @100kHz UNITS 19.44MHz -80 -108 -132 -142 -150 77.76MHz -72 -103 -122 -130 -125 155.52MHz -65 -95 -120 -125 -121 Phase Noise relative to carrier (typical) 622.08MHz -55 -85 -109 -115 -110 dBc/Hz Note: Phase Noise measured at VCON = 0V 7. CMOS Electrical Characteristics PARAMETERS SYMBOL CONDITIONS MIN. TYP. MAX. UNITS IOH VOH= VDD-0.4V, VDD=3.3V 10 mA Output drive current IOL VOL = 0.4V, VDD = 3.3V 10 mA Output Clock Rise/Fall Time 0.3V ~ 3.0V with 15 pF load 2.4 ns |
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