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PLL702-02OCL Datasheet(PDF) 6 Page - PhaseLink Corporation |
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PLL702-02OCL Datasheet(HTML) 6 Page - PhaseLink Corporation |
6 / 7 page PLL702-02 Low EMI Peripheral Clock Generator for Notebook & Motherboards 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 08/30/05 Page 6 3. DC Specifications PARAMETERS SYMBOL CONDITIONS MIN. TYP. MAX. UNITS Operating Voltage VDD Nominal voltage 3.3V 2.97 3.63 V Input High Voltage VIH VDD/2 V Input Low Voltage VIL VDD/2 VDD/2 - 1 V Input High Voltage VIH For all Tri-level input VDD-0.5 V Input Low Voltage VIL For all Tri-level input 0.5 V Input High Voltage VIH For all normal input 2 V Input Low Voltage VIL For all normal input 0.8 V IOH = -30mA (normal drive) Output High Voltage VOH IOH = -60mA (double drive) 2.4 V IOL = 30mA (normal drive) Output Low Voltage VOL IOH = -60mA (double drive) 0.4 V Output High Voltage At CMOS Level VOH IOH = -8mA VDD-0.4 V Normal drive strength 30 Nominal Output Current IOUT Double drive strength 60 mA Operating Supply Current IDD No Load 17 mA Short-circuit Current IS ±100 mA |
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