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PLL502-12SOM Datasheet(PDF) 1 Page - PhaseLink Corporation |
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PLL502-12SOM Datasheet(HTML) 1 Page - PhaseLink Corporation |
1 / 6 page Preliminary PLL502-12 96MHz – 200MHz Low Phase Noise LVDS VCXO (12 – 25MHz Crystals) 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 7/15/02 Page 1 FEATURES • Low phase noise output for the 96MHz to 200MHz range (-125 dBc at 10kHz offset). • LVDS output. • 12 to 25MHz crystal input. • Integrated crystal load capacitor: no external load capacitor required. • Output Enable selector. • Wide pull range (min. +/-190 ppm) • 3.3V operation. • Available in 16 Pin TSSOP or SOIC. DESCRIPTION The PLL502-12 is a monolithic low jitter and low phase noise (-125dBc/Hz @ 10kHz offset) VCXO IC with LVDS output, for 96MHz to 200MHz output range. It allows the control of the output frequency with an input voltage (VIN), using a low cost crystal. The chip provides a pullable output at a frequency of FXIN x 8. This makes the PLL502-12 ideal for a wide range of applications, including 155.52MHz for SONET. PIN CONFIGURATION FOUT = FXIN x 8 OE (Pin 5) Output State 0 Tri-state 1 (Default) Output enabled BLOCK DIAGRAM Reference Divider Phase Comparator Charge Pump Loop Filter VCO VCO Divider XTAL OSC CLKBAR OE XIN XOUT CLK VIN VARICAP 1 2 3 4 5 6 7 8 VDD 9 10 11 12 13 14 15 16 VDD XIN XOUT OE VIN GND GND VDD GND_BUF CLKBAR VDD_BUF CLK GND_BUF GND GND |
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