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PLL702-05SC-R Datasheet(PDF) 3 Page - PhaseLink Corporation |
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PLL702-05SC-R Datasheet(HTML) 3 Page - PhaseLink Corporation |
3 / 6 page PLL702-05 Low EMI Peripheral Clock Generator for Notebook 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 08/12/04 Page 3 recommended to use an external resistor of around one sixth to one quarter of the internal pull-up resistor (see Application Diagram). Note: when the output is used to drive a load presenting an small resistance between the output pin and VDD, this resistance is in essence connected in parallel to the internal pull-up resistor. In such a case, the external pull-down resistor may have to be dimensioned smaller to guarantee that the pin voltage will be low enough achieve the desired logical “zero”. This is particularly true when driving 74FXX TTL components. APPLICATION DIAGRAM: BI-DIRECTIONAL PINS WITH INTERNAL PULL-DOWN Latch Jumper options R DOWN/4 Clock Load Latched Input Output EN R down Tri-Level pin NOTE: Rdn=Internal pull-down resistor (see pin description). Power-up Reset : R starts from 1 to 0 while RB starts from 0 to 1. Internal to chip External Circuitry Power Up Reset R RB Jumper options Vcc Bi-directional pin |
Similar Part No. - PLL702-05SC-R |
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Similar Description - PLL702-05SC-R |
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