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P702-01XC Datasheet(PDF) 2 Page - PhaseLink Corporation |
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P702-01XC Datasheet(HTML) 2 Page - PhaseLink Corporation |
2 / 8 page PLL702-01 Clock Generator for PowerPC Based Applications 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 07/18/05 Page 2 PIN DESCRIPTIONS Name Number Type Description CPUDRV_SEL 1 I CPU drive strength selector pin. The CPU drive strength can be set to 67% of nominal strength with CPUDRV_SEL = 0. When CPUDRV_SEL = 1, the CPU drive strength will be 100% of the nominal strength. Internal pull-up of 60k Ω. 0=connect to GND, 1=leave open. XIN 2 I Crystal input to be connected to a 14.31818MHz fundamental crystal (CL = 20pF, parallel resonant mode). Load capacitors have been integrated on the chip. No external Load capacitor is required. XOUT/ ASIC2_OE 3 B Bi-directional pin. Upon power-on, the value of ASIC2_OE is latched in and used to enable / disable the ASIC2A and ASIC2B outputs (outputs are enabled if ASIC2_OE=1, otherwise, outputs are in tri-state). Internal pull-up of 120 k Ω. After the input has been latched-in, the pin serves as Crystal connection. VDD_ANA / GND_ANA VDD_DIG / GND_DIG 4, 5, 16, 24 P 3.3V power supply and GND. VDD_xxx / GND_xxx for USB, CPU, PCI, ASIC1 and ASIC2 6, 8, 9, 10, 12, 15, 18, 20, 21, 23 P CPU, PCI, ASIC1 and ASIC2 outputs have separate power supply pins (VDD and GND). VDD_CPU, VDD_ASIC1 and VDD_ASIC2 can accept 3.3V and/or 2.5V power supply. Other VDD pins are to be supplied 3.3V PCI / PCI_SEL 7 B Bi-directional pin. Upon power-on, the value of PCI_SEL is latched in and used to select the PCI clock output (see frequency table on p.1). PCI output is disabled (tri-state) when PCI_SEL=1. PCI clock will be 33MHz (min. 31.25MHz) if PCI_SEL=M (not connected), and 66MHz (min. 62.5MHz) if PCI_SEL=0. 0=15k Ω to GND, M=leave open, 1=15kΩ to VDD_PCI USB / USB_SEL 11 B Bi-directional pin. Upon power-on, the value of USB_SEL is latched in and used to select the USB output (see USB selection table on page 3). After the input has been latched-in, the pin serves as USB (48, 30 or 12 MHz) output. 0=15k Ω to GND, M=leave open, 1=15kΩ to VDD_USB ASIC2A and ASIC2B 13, 14 O ASIC clock signal output pins. ASIC2A and ASIC2B will have the same frequency as CPU. These outputs can be disabled through ASIC2_OE. ASIC1_SEL 17 I ASIC1 frequency select input pin (see also frequency table on p.1). ASIC1 will have the same frequency as CPU if ASIC1_SEL = 1, and have half of CPU if ASIC_SEL = 0. Internal pull-up of 60 k Ω. 0=connect to GND, 1=leave open ASIC1 19 O ASIC1 output pin (see frequency table on p.1 and ASIC1_SEL pin description). CPU 22 O CPU clock signal output pin. The CPU clock frequency is selected as per the frequency table on page 1, depending on the value of CLK_SEL(0:1). Selectable drive strength through CPUDRV_SEL. SSC(0:1) 25, 26 I Bi-level input with Pull-up for SST control (see Spread Spectrum selection table on p.3). 0=connect to GND, 1=leave open. CLK_SEL(0:1) 27, 28 I Tri-level inputs for CPU clock frequency selection (see table on p.1). 0=connect to GND, M=not connected, 1=connect to VDD_ANA. |
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