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PLL520-70DM Datasheet(PDF) 2 Page - PhaseLink Corporation |
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PLL520-70DM Datasheet(HTML) 2 Page - PhaseLink Corporation |
2 / 5 page Preliminary PLL520-70 CMOS Low Phase Noise VCXO (for 45-90MHz Fund Xtal) 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 8/26/02 Page 2 ELECTRICAL SPECIFICATIONS 1. Absolute Maximum Ratings PARAMETERS SYMBOL MIN. MAX. UNITS Supply Voltage VDD 7 V Input Voltage, dc VI VSS-0.5 VDD+0.5 V Output Voltage, dc VO VSS-0.5 VDD+0.5 V Storage Temperature TS -65 150 °C Ambient Operating Temperature* TA -40 85 °C Junction Temperature TJ 125 °C Lead Temperature (soldering, 10s) 260 °C Input Static Discharge Voltage Protection 2 kV Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above the operational limits noted in this specification is not implied. * Note: Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for INDUSTRIAL grade only. 2. Crystal Specifications 3. Voltage Control Crystal Oscillator PARAMETERS SYMBOL CONDITIONS MIN. TYP. MAX. UNITS VCXO Stabilization Time * TVCXOSTB From power valid 10 ms VCXO Tuning Range XTAL C0/C1 < 250 200* ppm CLK output pullability 0V ≤ VCON ≤ 3.3V at room temperature ±100* ppm On-chip Varicaps control range VCON = 0 to 3.3V 4 – 18* pF Linearity 5* 10* % VCXO Tuning Characteristic 65 ppm/V VCON input impedance 60 k Ω VCON modulation BW 0V ≤ VCON ≤ 3.3V, -3dB 25 kHz Note: Parameters denoted with an asterisk (*) represent nominal characterization data and are not production tested to any specific limits. PARAMETERS SYMBOL CONDITIONS MIN. TYP. MAX. UNITS CX+ 2 Built-in Capacitance CX- 2 Inter-electrode capacitance C0 45MHz to 90MHz (VDD=3.3V) 3.6 pF C0/C1 ratio (gamma) γ 250 - Oscillation Frequency OF Fund. 45 90 MHz |
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