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PLL620-30DI Datasheet(PDF) 4 Page - PhaseLink Corporation |
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PLL620-30DI Datasheet(HTML) 4 Page - PhaseLink Corporation |
4 / 6 page PLL620-30 PECL and LVDS Low Phase Noise XO (32.5 to 130MHz output) 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 11/09/04 Page 4 8. PECL Electrical Characteristics PARAMETERS SYMBOL CONDITIONS MIN. MAX. UNITS Output High Voltage VOH VDD – 1.025 VDD – 0.750 V Output Low Voltage VOL RL = 50 Ω to (VDD – 2V) (see figure) VDD – 1.900 VDD – 1.620 V 9. PECL Switching Characteristics PARAMETERS SYMBOL CONDITIONS MIN. TYP. MAX. UNITS Clock Rise Time tr @20/80% - PECL 0.3 0.6 1.5 ns Clock Fall Time tf @80/20% - PECL 0.3 0.5 1.5 ns OUT OUT 50 Ω 50 Ω PECL Levels Test Circuit PECL Transistion Time Waveform OUT OUT 50% 20% 80% t R t F VDD DUTY CYCLE 45 - 55% 55 - 45% 50% OUT OUT t SKEW PECL Output Skew 2.0V |
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