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PLL602-39OILR Datasheet(PDF) 2 Page - PhaseLink Corporation |
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PLL602-39OILR Datasheet(HTML) 2 Page - PhaseLink Corporation |
2 / 8 page PLL602-35/-37/-38/-39 750kHz – 800MHz Low Phase Noise Multiplier XO Universal Low Phase Noise IC’s 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 11/28/05 Page 2 FREQUENCY SELECTION TABLE SEL3 SEL2 SEL1 SEL0 Selected Multiplier 0 0 1 1 Fin x 32 0 1 1 0 Fin / 8 0 1 1 1 Fin x 2 1 0 0 1 Fin / 2 1 0 1 0 Fin / 16 1 0 1 1 Fin x 4 1 1 0 0 Fin / 4 1 1 0 1 Fin x 8 1 1 1 0 Fin x 16 1 1 1 1 No multiplication Note: SEL0 is not available (always “1”) for PLL602-35 and PLL602-38 in 3x3mm package PIN DESCRIPTIONS PLL602-35 and PLL602-38 (see next page of PLL602-37/-39) Name TSSOP Pin number 3x3mm QFN Pin number Type Description XIN 2 12 I Crystal input. See Crystal Specifications on page 3. XOUT 3 13 I Crystal output. See Crystal Specifications on page 3. OE 6 16 I Output enable pin (see OE logic state table on page 1). GND 7,8,9,10,14 1,2,3,4,8,11 P Ground. CLKT 11 5 O True output PECL CLKC 13 7 O Complementary output PECL. SEL0 16 Not available I SEL1 15 9 I SEL2 5 15 I SEL3 4 14 I Multiplier selector pins. These pins have an internal pull-up that will default SEL to ‘1’ when not connected to GND. VDD 1, 12 6,10 P Power Supply. |
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