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PLL650-05BILR Datasheet(PDF) 4 Page - PhaseLink Corporation

Part # PLL650-05BILR
Description  Low EMI Network LAN Clock
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Manufacturer  PLL [PhaseLink Corporation]
Direct Link  http://www.phaselink.com
Logo PLL - PhaseLink Corporation

PLL650-05BILR Datasheet(HTML) 4 Page - PhaseLink Corporation

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PLL650-05
Low EMI Network LAN Clock
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/03/04 Page 4
Electrical Specifications
1. Absolute Maximum Ratings
PARAMETERS
SYMBOL
MIN.
MAX.
UNITS
Supply Voltage
VDD
4.6
V
Input Voltage, dc
VI
-0.5
VDD+0.5
V
Output Voltage, dc
VO
-0.5
VDD+0.5
V
Storage Temperature
TS
-65
150
°C
Ambient Operating Temperature*
TA
-40
85
°C
Junction Temperature
TJ
125
°C
Lead Temperature (soldering, 10s)
260
°C
ESD Protection, Human Body Model
2
kV
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device
and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above
the operational limits noted in this specification is not implied.
* Note: Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for COMMERCIAL grade only.
2. AC Specifications
PARAMETERS
CONDITIONS
MIN.
TYP.
MAX.
UNITS
Input Frequency
10
25
27
MHz
Output Rise Time
0.8V to 2.0V with no load
1.5
ns
Output Fall Time
2.0V to 0.8V with no load
1.5
ns
Duty Cycle*
@ 50% VDD
45
50
55
%
Max. Absolute Jitter
Short term
±150
ps
Max. Jitter, cycle to cycle
80
ps
* : in case SDRAM output is selected to be 83.3MHz, the duty cycle of output pin 22 will be 40%-60% if its output frequency is selected to be 105MHz
(FS2=1). In all other situations, pin 22 will also have a 50%-50% typical duty cycle.


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