PLL620-05/-06/-07/-08/-09
Low Phase Noise XO with multipliers (for 100-200MHz Fund or 3rdOT Xtal)
Universal Low Phase Noise IC’s
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 11/01/05 Page 2
PIN DESCRIPTIONS
Name
TSSOP*
Pin number
3x3mm QFN*
Pin number
Type
Description
VDD
1, 12
6,11
P
+3.3V power supply.
XIN
2
13
I
Crystal input. See Crystal Specification on page 3.
XOUT
3
14
I
Crystal output. See Crystal Specification on page 3.
OE
6
16
I
Output enable.
GND
7,8,9, 10, 14
1,2,3,4,8
P
Ground (except pin 12 on PLL620-06: DRIVSEL see below).
DRIVSEL**
-
12
I
PLL620-06 only: Drive Select Input. This pin has an internal
pull-up that will default DRIVSEL to ‘1’ when not connect to
GND. CMOS output of PLL620-06 will be high drive CMOS
when DRIVSEL is set to ‘0’, and will be standard CMOS
otherwise. The pin remains ‘Do Not Connect (DNC)’ for
PLL620-05/07/08/09.
CLKT
11
5
O
True output PECL (PLL620-08) or LVDS (PLL620-09)
(N/C for PLL620-07)
CLKC
13
7
O
Complementary output PECL (PLL620-08) or LVDS (PLL620-
09)
(CMOS out for PLL620-07).
SEL0
16
10
I
SEL1
15
9
I
SEL2
5
15
I
SEL3
4
Not available
I
Multiplier selector pins. These pins have an internal pull-up
that will default SEL to ‘1’ when not connected to GND.
* Note: PLL620-06 only available in 3x3mm QFN, PLL620-07 only available in TSSOP.
** Note: DRIVSEL on pin 12 on PLL620-06 only. The pin remains ‘Do Not Connect (DNC)’ for PLL620-05/07/08/09.
FREQUENCY SELECTION TABLE
SEL3
SEL2
SEL1
SEL0
Selected Multiplier
0
0
1
1
Fin x 8(PLL620-09 only)
1
0
1
1
Fin x 4
1
1
1
0
Fin x 2
1
1
1
1
No multiplication
Note: SEL3 is not available (always “1”) in 3x3mm package
All pins have internal pull-ups (default value is 1). Connect to GND to set to 0.
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