PLL601-15 datasheet(4/5 Pages) PLL | Low Phase Noise PLL Clock Multiplier

Part Name

Description

PLL601-15

Low Phase Noise PLL Clock Multiplier ( 5 Page)

PLL

4 page

Preliminary

PLL601-15

Low Phase Noise PLL Clock Multiplier

47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991

Rev 01/08/02 Page 4

3. DC Specification

PARAMETERS

SYMBOL

CONDITIONS

MIN.

TYP.

MAX.

UNITS

Operating Voltage

VDD

3.135

3.465

Input High Voltage

VIH

Input Low Voltage

VIL

0.8

Input High Voltage

VIH

For XIN pin

(VDD/2)

+ 1

VDD/2

Input Low Voltage

VIL

For XIN pin

VDD/2

(VDD/2)

− 1

Output High Voltage

VOH

IOH = -25mA

2.4

Output Low Voltage

VOL

IOL = 25mA

0.4

Output High Voltage At

CMOS Level

VOH

IOH = -8mA

VDD-0.4

Operating Supply Current

IDD

No Load

Short-circuit Current

±120

4. Crystal Specifications

PARAMETERS

SYMBOL

CONDITIONS

MIN.

TYP.

MAX.

UNITS

Crystal Resonator Frequency

FXIN

Parallel Fundamental Mode

MHz

Crystal Loading Capacitance

Rating

CL (xtal)

Html Pages

1 2 3 4 5

Datasheet Download

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