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AS7C33256PFS18A-150TQI Datasheet(PDF) 1 Page - Alliance Semiconductor Corporation |
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AS7C33256PFS18A-150TQI Datasheet(HTML) 1 Page - Alliance Semiconductor Corporation |
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1 / 11 page  March 2001 Copyright © Alliance Semiconductor. All rights reserved. AS7C33256PFS16A AS7C33256PFS18A 3.3V 256K ×××× 16/18 pipeline burst synchronous SRAM ® 3/14/01; V.1.0 Alliance Semiconductor P. 1 of 11 Features • Organization: 262,144 words × 16 or 18 bits • Fast clock speeds to 166 MHz in LVTTL/LVCMOS • Fast clock to data access: 3.5/3.8/4.0/5.0 ns •Fast OE access time: 3.5/3.8/4.0/5.0 ns • Fully synchronous register-to-register operation • “Flow-through” mode • Single-cycle deselect - Dual-cycle deselect also available (AS7C33256PFD16A/ AS7C33256PFD18A) •Pentium® * compatible architecture and timing • Asynchronous output enable control • Economical 100-pin TQFP package • Byte write enables • Multiple chip enables for easy expansion • 3.3V core power supply • 2.5V or 3.3V I/O operation with separate VDDQ • 30 mW typical standby power in power down mode •NTD™* pipeline architecture available (AS7C33256NTD16A/AS7C33256NTD18A) Selection guide *Pentium® is a registered trademark of Intel Corporation. NTD™ is a trademark of Alliance Semiconductor Corporation. All trademarks mentioned in this document are the property of their respective owners. AS7C33256PFS16A –166 AS7C33256PFS16A –150 AS7C33256PFS16A –133 AS7C33256PFS16A –100 Units Minimum cycle time 6 6.7 7.5 10 ns Maximum pipelined clock frequency 166 150 133 100 MHz Maximum pipelined clock access time 3.5 3.8 4 5 ns Maximum operating current 475 450 425 325 mA Maximum standby current 130 110 100 90 mA Maximum CMOS standby current (DC) 30 30 30 30 mA Logic block diagram Burst logic ADV ADSC ADSP CLK LBO CLK CLR CS 18 16 18 A[17:0] 18 Address D Q CS CLK register 256K × 16/18 Memory array 16/18 16/18 DQb CLK DQ Byte Write registers DQa CLK DQ Byte Write registers Enable CLK DQ register Enable CLK DQ delay register CE Output registers Input registers Power down DATA [17:0] 2 CE0 CE1 CE2 BWb BWa OE ZZ OE FT CLK CLK DATA [15:0] BWE GWE Pin arrangement NC NC NC VDDQ VSSQ NC NC DQb DQb VSSQ VDDQ DQb DQb FT VDD NC VSS DQb DQb VDDQ VSSQ DQb DQb DQpb/NC NC VSSQ VDDQ NC NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 A17 NC NC VDDQ VSSQ NC DQpa/NC DQa DQa VSSQ VDDQ DQa DQa VSS ZZ DQa DQa VDDQ VSSQ DQa DQa NC NC VSSQ VDDQ NC NC NC NC VDD TQFP 14 × 20mm Note: pins 24, 74 are NC for ×16. |
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