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IDT72V3612L20PF Datasheet(PDF) 1 Page - Integrated Device Technology |
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IDT72V3612L20PF Datasheet(HTML) 1 Page - Integrated Device Technology |
1 / 25 page 1 3.3 VOLT CMOS SyncBiFIFOTM 64 x 36 x 2 IDT72V3612 1 MAY 2003 2003 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. DSC-4659/1 IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. SyncBiFIFO is a trademark of Integrated Device Technology, Inc. COMMERCIAL TEMPERATURE RANGE FEATURES: ••••• Two independent clocked FIFOs (64 x 36 storage capacity each) buffering data in opposite directions • Supports clock frequencies up to 83 MHz ••••• Fast access times of 8ns ••••• Free-running CLKA and CLKB can be asynchronous or coincident (simultaneous reading and writing of data on a single clock edge is permitted) • Mailbox bypass Register for each FIFO • Programmable Almost-Full and Almost-Empty Flags • Microprocessor interface control logic • EFA , FFA , AEA , and AFA flags synchronized by CLKA • EFB , FFB , AEB , and AFB flags synchronized by CLKB • Passive parity checking on each port • Parity generation can be selected for each port • Available in 132-pin plastic quad flat package (PQF), or space saving 120-pin thin quad flat package (TQFP) • Pin and functionally compatible version of the 5V operating IDT723612 • Industrial temperature range (–40 °°°°°C +85°°°°°C) is available DESCRIPTION: The IDT72V3612 is a pin and functionally compatible version of the IDT723612, designed to run off a 3.3V supply for exceptionally low-power consumption. This device is a monolithic high-speed, low-power CMOS bi- directional clocked FIFO memory. It supports clock frequencies up to 83 MHz FUNCTIONAL BLOCK DIAGRAM Mail 1 Register CLKA CSA W/ RA ENA MBA Port-A Control Logic Device Control RST CLKB CSB W/ RB ENB MBB Port-B Control Logic MBF1 4659 drw 01 Mail 2 Register Write Pointer Read Pointer Status Flag Logic Parity Gen/Check A0 - A35 36 RAM ARRAY 64 x 36 Parity Gen/Check Programmable Flag Offset Register Status Flag Logic RAM ARRAY 64 x 36 Read Pointer PEFB PGB EFB AEB FFB AFB ODD/ EVEN FFA AFA FS0 FS1 EFA AEA PGA PEFA MBF2 Write Pointer FIFO2 FIFO1 36 36 B0 - B36 |
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