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U4091BM-NFN Datasheet(PDF) 8 Page - ATMEL Corporation |
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U4091BM-NFN Datasheet(HTML) 8 Page - ATMEL Corporation |
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8 / 38 page  8 U4091BM-N 4666B–CORD–08/04 Clock Output Divider Adjustment The Pin OSCOUT is a clock output which is derived from the crystal oscillator. It can be used to drive a micro-controller or another remote component and thereby reduces the number of crystals required. The oscillator frequency can be divided by 1, 8, 16, 32. Dur- ing power-on reset, the divider will be reset to 1 until it is changed by setting the serial bus. Table 2. Clock Output Serial Bus Interface The circuit is controlled by an external microcontroller through the serial bus. The serial bus is a bi-directional system consisting of a one-directional clock line (SCL) which is always driven by the microcontroller, and a bi-directional data-signal line. It is driven by the microcontroller as well as from the U4091BM-N (see Figure 24 on page 37). The serial bus requires external pull-up resistors as only pull-down transistors (Pin SDA) are integrated. WRITE The data is a 12-bit word: A0 - A3: address of the destination register (0 to 15) D0 - D7: content of the register The data line must be stable when the clock is high. Data must be shifted serially. After 12 clock periods, the write indication is sent. Then, the transfer to the destination register is (internally) generated by a strobe signal transition of the data line when the clock is high. READ There is a normal and a fast-read cycle. In the normal read cycle, the microcontroller sends a 4-bit address followed by the read indicator, then an 8-bit word is read out. The U4091BM-N drives the data line. The fast read cycle is indicated by a strobe signal. With the following two clocks the U4091BM-N reads out the status bits RFDO and LIDET which indicate that a ringing signal or a line signal is present (see Figure 5 on page 11, Figure 6 on page 11 and Fig- ure 7 on page 11). DTMF Dialing The DTMF generator sends a multi-frequency signal through the matrix to the line. The signal is the result of the sum of two frequencies and is internally filtered. The frequen- cies are chosen from a low and a high frequency group. The circuit conforms to the CEPT recommendation concerning DTMF option. Three different levels for the low level group and two different pre-emphasis (2.5 dB and 3.5 dB) can be chosen by means of the serial bus (rec. T/CF 46-03). Attention: In high gain mode distortion can occur, if AGATX is high and DC mask is low. CLK[0:1] Divider Frequency 01 3.58 MHz 18 447 kHz 216 224 kHz 332 112 kHz |
Similar Part No. - U4091BM-NFN |
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Similar Description - U4091BM-NFN |
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