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JL139BDA Datasheet(PDF) 7 Page - National Semiconductor (TI) |
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JL139BDA Datasheet(HTML) 7 Page - National Semiconductor (TI) |
7 / 20 page LM139 JAN Electrical Characteristics (Continued) DC Parameters Drift Values The following conditions apply, unless otherwise specified. −V CC =0V Delta calculations performed on JAN S product at Group B, Subgroup 5. Symbol Parameters Conditions Notes Min Max Unit Sub- groups V IO Input Offset Voltage V CC = 30V,VO = 15V -1.0 1.0 mV 1 +/- I Bias Input Bias Current V CC = 30V,RS = 20K Ω, V O = 15V -15 15 nA 1 Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not guaranteed specific performance limits. For guaranteed specifications and test conditions, see, the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions. Note 2: Short circuits from the output to V+ can cause excessive heating and eventual destruction. When considering short circuits to ground, the maximum output current is approximately 20 mA independent of the magnitude of V+. Note 3: This input current will only exist when the voltage at any of the input leads is driven negative. It is due to the collector-base junction of the input PNP transistors becoming forward biased and thereby acting as input diode clamps. In addition to this diode action, there is also lateral NPN parasitic transistor action on the IC chip. This transistor action can cause the output voltages of the comparators to go to the V+ voltage level (or to ground for a large overdrive) for the time duration that an input is driven negative. This is not destructive and normal output states will re-establish when the input voltage, which was negative, again returns to a value greater than −0.3 VDC (at 25˚)C. Note 4: The low bias dissipation and the ON-OFF characteristics of the outputs keeps the chip dissipation very small (PD ≤ 100mW), provided the output transistors are allowed to saturate. Note 5: The direction of the input current is out of the IC due to the PNP input stage. This current is essentially constant, independent of the state of the outputso no loading change exists on the reference or input lines. Note 6: Short circuits from the output to V+ can cause excessive heating and eventual destruction. When considering short circuits to ground, the maximum output current is approximately 20mA independent of the magnitude of V+ Note 7: Positive excursions of input voltage may exceed the power supply level. As long as the other voltage remains within the common-mode range, the comparator will provide a proper output state. The low input voltage state must not be less than −0.3 VDC (or 0.3 VDCbelow the magnitude of the negative power supply, if used) (at 25˚C). Note 8: S/S RS = 20KΩ, tested at RS = 10KΩ as equivalent test. Note 9: Calculated parameter; for Delta VIO / Delta T use VIO test at +VCC = 30V, −VCC =0V, VO = 15V; and for Delta IIO / Delta T use IIB test at +VCC = 30V, −VCC =0V, VO = 15V Note 10: Datalog of K = V/mV. Note 11: Human Body model, 1.5 K Ω in series with 100 pF Note 12: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJmax (maximum junction temperature), θJA (Package junction to ambient thermal resistance), and TA (ambient temperature). The maximum allowable power dissipation at any temperature is PDmax =(TJmax —TA)/ θJA or the number given in the Absolute Maximum Ratings, whichever is lower. www.national.com 7 |
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