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XRD9836 Datasheet(PDF) 10 Page - Exar Corporation |
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XRD9836 Datasheet(HTML) 10 Page - Exar Corporation |
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10 / 32 page  XRD9836 xr xr 16-BIT PIXEL GAIN AFE REV. 1.0.0 10 SYSTEM OVERVIEW The XRD9836 provides a 16-bit Analog Front End functionality for Mid-to-High range, next-generation scanner applications. It has 3 channels of Correlated Double Sampling (CDS), using a 10-bit Dynamic Off- set DAC, a 10-bit Programmable Gain Amplifier (PGA) and a 10-bit Fine Offset DAC for Red, Green, and Blue CCD signals. A 16-bit 30MHz ADC is multi- plexed among these 3 channels to provide digitized image data for the scanner ASIC chip. In 3-channel mode, the order of channels is R, G, B. In the 1-chan- nel mode, only the selected channel is active. The XRD9836 provides one of the key requirements for the next generation scanner AFE’s, the ability to con- trol Pixel-by-Pixel Gain and Offset values. Figure 3 shows the ASIC and AFE interface for the proposed system. A 10-bit parallel bus Offset Gain Input Port (OGI) is used to transfer 10 bits of Gain and 10 bits of Offset. In the 3-channel mode, the data is received sequen- tially in the following order: red gain, red offset, green gain, green offset, blue gain, blue offset. In 1-channel mode, the data is received sequentially gain then off- set. For an example of both 3-channel and 1-channel OGI timing see Figure 4. The Input Enable pin (IE) enables OGI port to pro- gram internal pixel gain and offset registers. If IE goes low, the gain and offset registers will store the last data while IE was high. For ADC outputs, the XRD9836 has an 8-bit parallel bus ADC Data Out (ADCDO). The ADC output data is transmitted sequentially in the following order for 3-ch mode red high order byte, red low order byte, green high order byte, green low order byte, blue high order byte, blue low order byte as shown in Figure 5 A three-pin, Micro-controller Serial I/O link (uSIO) is used to write or read from the XRD9836’s internal configuration registers. The internal registers control the various modes of operation of the chip. FIGURE 3. SYSTEM BLOCK DIAGRAM |
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