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TMS320C6203BGNY300 Datasheet(PDF) 7 Page - Texas Instruments |
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TMS320C6203BGNY300 Datasheet(HTML) 7 Page - Texas Instruments |
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7 / 106 page  TMS320C6203B FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS086M − JANUARY 1999 − REVISED MARCH 2004 7 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 functional and CPU (DSP core) block diagram 32 Multichannel Buffered Serial Port 1 32 Direct Memory Access Controller (DMA) (See Table 1) Test C62x CPU (DSP Core) Data Path B B Register File Program Access/Cache Controller Instruction Fetch Instruction Dispatch Instruction Decode Data Path A A Register File PLL (x1, x4, x6, x7, x8, x9, x10, x11)† Data Access Controller Power- Down Logic .L1 .S1 .M1 .D1 .D2 .M2 .S2 .L2 SDRAM or SBSRAM ROM/FLASH SRAM I/O Devices Synchronous FIFOs I/O Devices Timer 0 Timer 1 External Memory Interface (EMIF) Multichannel Buffered Serial Port 0 Multichannel Buffered Serial Port 2 Expansion Bus (XBus) 32-Bit Internal Program Memory: 1 Block Program (256K Bytes) 1 Block Program/Cache (128K Bytes) Control Registers Control Logic Internal Data Memory (512K Bytes) In-Circuit Emulation Interrupt Control Framing Chips: H.100, MVIP, SCSA, T1, E1 AC97 Devices, SPI Devices, Codecs HOST CONNECTION Master /Slave TI PCI2040 Power PC 683xx 960 C6203B Digital Signal Processor Peripheral Control Bus Boot Configuration Interrupt Selector † For additional details on the PLL clock module and specific options for the C6203B device, see Table 1 and the Clock PLL section of this data sheet. |
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