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NT256S72V89A0G
256MB : 32M x 72
Unbuffered SDRAM Module
Preliminary 09 / 2001
9
© NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
Read Cycle
- 7K
- 75B
- 8B
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
Note
-
-
-
-
2.5
-
ns
tOH
Data Out Hold Time
2.7
-
2.7
-
3
-
ns
tLZ
Data Out to Low Impedance Time
0
-
0
-
0
-
ns
tHZ3
Data Out to High Impedance Time
3
5.4
3
5.4
3
6
ns
1
tDQZ
DQM Data Out Disable Latency
2
-
2
-
2
-
CLK
1.
Referenced to the time at which the output achieves the open circuit condition, not to output voltage levels.
Refresh Cycle
- 7K
- 75B
- 8B
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
Note
tREF
Refresh Period
-
64
-
64
-
64
ms
tSREX
Self Refresh Exit Time
10
-
10
-
10
-
ns
Write Cycle
- 7K
- 75B
- 8B
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
Note
tDS
Data In Set-up Time
1.5
-
1.5
-
2
-
ns
tDH
Data In Hold Time
0.8
-
0.8
-
1
-
ns
tDPL
Data input to Precharge
15
-
15
-
15
-
ns
tDAL3
Data In to Active Delay
CAS Latency = 3
5
-
5
-
5
-
CLK
tDAL2
Data In to Active Delay
CAS Latency = 2
5
-
-
-
-
-
CLK
tDQW
DQM Write Mask Latency
0
-
0
-
0
-
ns
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